diff options
| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-24 13:48:13 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-28 12:08:53 -0700 |
| commit | 49cdce163519ad760ca7769be64dd2a6133a5c11 (patch) | |
| tree | 59768dd593800b2a9f56336a72beb05d4fd8dd8a /arch/arm | |
| parent | 1483151e84161449c3f652a751a04e06b0723bff (diff) | |
armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 14 |
3 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d8ec426ce2..f62b78d102 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has DP_DDR */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; @@ -40,7 +40,7 @@ bool soc_has_aiop(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has AIOP */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index df877ddc7d..197b0eb5a5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,13 +8,13 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), - CPU_TYPE_ENTRY(LS1043, LS1043, 4), - CPU_TYPE_ENTRY(LS1023, LS1023, 2), - CPU_TYPE_ENTRY(LS2040, LS2040, 4), - CPU_TYPE_ENTRY(LS1012, LS1012, 1), + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 2cb6c5430e..39e8c7a17c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -41,13 +41,13 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012 0x870400 -#define SVR_LS1043 0x879200 -#define SVR_LS1023 0x879208 -#define SVR_LS2045 0x870120 -#define SVR_LS2080 0x870110 -#define SVR_LS2085 0x870100 -#define SVR_LS2040 0x870130 +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) |