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authorMichal Simek <michal.simek@xilinx.com>2018-02-21 15:06:20 +0100
committerMichal Simek <michal.simek@xilinx.com>2018-03-23 09:34:43 +0100
commit58afff43e3a8f31344cbbc6a3f09bd3f7a2a70eb (patch)
treef455d56690cba8e4c9062d55c7b8dce40888d29a /arch/arm
parent1cf6cac4d16ef5e9f7c0fa9cd62275924626a130 (diff)
clk: zynq: Show watchdog clock rate properly
watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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