diff options
| author | MarkLee <Mark-MC.Lee@mediatek.com> | 2020-01-21 19:31:59 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-02-07 13:59:58 -0500 |
| commit | 6efa450565cdc9c178bb2be033d2ba153c736749 (patch) | |
| tree | 583cdbb624f3503e8ad5a4fb79c6a7e0a9fde3a5 /arch/arm | |
| parent | e395717ca9f347d46330fb479b779cd32915cecd (diff) | |
arm: dts: mediatek: add ethernet and sgmii dts node for mt7622
This patch add eth and sgmii dts node for mt7622 to support ethernet
Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/mt7622-rfb.dts | 13 | ||||
| -rw-r--r-- | arch/arm/dts/mt7622.dtsi | 45 |
2 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index ec30f5c6eb..f05c3fe14d 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -178,3 +178,16 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 7dcca5c6af..1e8ec9b48b 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -7,6 +7,9 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7622-clk.h> +#include <dt-bindings/power/mt7629-power.h> +#include <dt-bindings/reset/mt7629-reset.h> +#include <dt-bindings/gpio/gpio.h> / { compatible = "mediatek,mt7622"; @@ -182,4 +185,46 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7622-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7622-eth", "syscon"; + reg = <0x1b100000 0x20000>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <&sgmiisys CLK_SGMII_TX250M_EN>, + <&sgmiisys CLK_SGMII_RX250M_EN>, + <&sgmiisys CLK_SGMII_CDR_REF>, + <&sgmiisys CLK_SGMII_CDR_FB>, + <&topckgen CLK_TOP_SGMIIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "esw", "gp0", "gp1", "gp2", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", + "eth2pll"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", "syscon"; + reg = <0x1b128000 0x3000>; + #clock-cells = <1>; + }; + }; |