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authorPeng Fan <peng.fan@nxp.com>2017-08-08 16:21:38 +0800
committerStefano Babic <sbabic@denx.de>2017-08-16 12:43:04 +0200
commit7236297aee8c0ef1b2e6c806725486b24ef16dc1 (patch)
treeb31c508b52978533c9132da878fdfcd851316b8e /arch/arm
parent79a57b5ae158e4d561b016e4e0aeef03c2d1d457 (diff)
imx: mx6sx: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-imx/mx6/soc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index e87a21513e..48eaa84921 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -379,6 +379,8 @@ static void set_preclk_from_osc(void)
int arch_cpu_init(void)
{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
init_aips();
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
@@ -448,6 +450,9 @@ int arch_cpu_init(void)
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+ if (is_mx6sx())
+ setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
+
init_src();
return 0;