diff options
author | Kever Yang <kever.yang@rock-chips.com> | 2017-02-23 15:37:51 +0800 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2017-03-16 16:03:46 -0600 |
commit | 85a3cfb80aeda3500e32816f2d9c9ec66bf3b50e (patch) | |
tree | 3ae5c70ee56d89d5cf737f1896d86eaf93cc5dde /arch/arm | |
parent | e94ffee335f23d86cad0f8816b049bb4100d5be3 (diff) |
rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 11 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3328/Kconfig | 0 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3328/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3328/rk3328.c | 39 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 20 |
6 files changed, 79 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 565908af34..bf8e6be410 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -38,6 +38,16 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3328 + bool "Support Rockchip RK3328" + select ARM64 + help + The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. + including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two + video interfaces supporting HDMI and eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 @@ -70,5 +80,6 @@ config SPL_MMC_SUPPORT source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" +source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 151fa2d144..6b251c7e7e 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -28,4 +28,5 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/Kconfig diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile new file mode 100644 index 0000000000..8ecf8eed1c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3328.o +obj-y += syscon_rk3328.o diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c new file mode 100644 index 0000000000..857f0142b0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> + +static struct mm_region rk3328_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3328_mem_map; + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c new file mode 100644 index 0000000000..a1a368fcd2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id rk3328_syscon_ids[] = { + { .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF }, +}; + +U_BOOT_DRIVER(syscon_rk3328) = { + .name = "rk3328_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3328_syscon_ids, +}; |