Merge git://www.denx.de/git/u-boot-marvell

14 files changed, 397 insertions, 126 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4d656ce4cc..4528a8ff42 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-385-amc.dtb			\
 	armada-7040-db.dtb			\
+	armada-7040-db-nand.dtb			\
 	armada-8040-db.dtb			\
 	armada-8040-mcbin.dtb			\
 	armada-xp-gp.dtb			\
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
index a5a8a7f186..4649c910c7 100644
--- a/arch/arm/dts/armada-385-amc.dts
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -54,6 +54,7 @@
 	aliases {
 		ethernet0 = &eth0;
 		ethernet1 = &eth1;
+		i2c0 = &i2c0;
 		spi1 = &spi1;
 	};
 
@@ -68,6 +69,8 @@
 
 		internal-regs {
 			i2c@11000 {
+				clock-frequency = <100000>;
+				u-boot,i2c-slave-addr = <0x0>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2c0_pins>;
 				status = "okay";
diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
new file mode 100644
index 0000000000..3a9df21a8c
--- /dev/null
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: NAND, 0xE (SW3)
+ */
+
+#include "armada-7040.dtsi"
+
+/ {
+	model = "Marvell Armada 7040 DB board with NAND";
+	compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
+		     "marvell,armada7040", "marvell,armada-ap806-quad",
+		     "marvell,armada-ap806";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cpm_i2c0;
+		spi0 = &cpm_spi1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&ap_pinctl {
+	   /* MPP Bus:
+	    * SDIO  [0-5]
+	    * UART0 [11,19]
+	    */
+		  /* 0   1   2   3   4   5   6   7   8   9 */
+	pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
+		     0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+
+&cpm_pcie2 {
+	status = "okay";
+};
+
+&cpm_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&cpm_pinctl {
+		/* MPP Bus:
+		 * AUDIO   [0-5]
+                 * GBE     [6-11]
+		 * SS_PWDN [12]
+		 * NF_RBn  [13]
+                 * GPIO    [14]
+		 * DEV_BUS [15-27]
+		 * SATA1   [28]
+		 * UART0   [29-30]
+		 * MSS_VTT_EN [31]
+		 * SMI	   [32,34]
+		 * XSMI    [35-36]
+		 * I2C	   [37-38]
+		 * RGMII1  [44-55]
+		 * SD	   [56-61]
+		 * GPIO    [62]
+		 */
+		 /*   0   1   2   3   4   5   6   7   8   9 */
+	 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
+		      0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
+		      0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
+		      0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
+		      0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
+		      0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
+		      0xe 0xe 0x0>;
+};
+
+&cpm_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_spi0_pins>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <20000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x200000>;
+			};
+
+			partition@400000 {
+				label = "Filesystem";
+				reg = <0x200000 0xe00000>;
+			};
+		};
+	};
+};
+
+&cpm_sata0 {
+	status = "okay";
+};
+
+&cpm_usb3_0 {
+	status = "okay";
+};
+
+&cpm_usb3_1 {
+	status = "okay";
+};
+
+&cpm_comphy {
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SGMII0>;
+		phy-speed = <PHY_SPEED_1_25G>;
+	};
+
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy4 {
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&cpm_nand {
+	status = "okay";
+};
+
+&cpm_utmi0 {
+	status = "okay";
+};
+
+&cpm_utmi1 {
+	status = "okay";
+};
+
+&ap_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
+
+&cpm_sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+};
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 84e0dbdc3d..b140b3476e 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -42,6 +42,7 @@
 
 /*
  * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: SPI NOR, 0x32 (SW3)
  */
 
 #include "armada-7040.dtsi"
@@ -158,7 +159,7 @@
 
 &cpm_comphy {
 	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
+		phy-type = <PHY_TYPE_SGMII1>;
 		phy-speed = <PHY_SPEED_1_25G>;
 	};
 
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index f1f196f563..fa589956ad 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -83,28 +83,68 @@
 
 &cpm_pinctl {
 	/* MPP Bus:
-	 * [0-31] = 0xff: Keep default CP0_shared_pins:
-	 * [11] CLKOUT_MPP_11 (out)
-	 * [23] LINK_RD_IN_CP2CP (in)
-	 * [25] CLKOUT_MPP_25 (out)
-	 * [29] AVS_FB_IN_CP2CP (in)
-	 * [32,34] SMI
-	 * [31]    GPIO: push button/Wake
-	 * [35-36] GPIO
-	 * [37-38] I2C
-	 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
-	 * [42-43] XSMI
-	 * [44-55] RGMII1
-	 * [56-62] SD
+	 *	[0-31]	= 0xff: Keep default CP0_shared_pins
+	 *	[11]	CLKOUT_MPP_11 (out)
+	 *	[23]	LINK_RD_IN_CP2CP (in)
+	 *	[25]	CLKOUT_MPP_25 (out)
+	 *	[29]	AVS_FB_IN_CP2CP (in)
+	 *	[32,34]	GE_MDIO/MDC
+	 *	[33]	GPIO: GE_INT#/push button/Wake
+	 *	[35]	MSS_GPIO[3]: MSS_PWDN
+	 *	[36]	MSS_GPIO[5]: MSS_VTT_EN
+	 *	[37-38]	I2C0
+	 *	[39]	PTP_CLK
+	 *	[40-41]	SATA[0/1]_PRESENT_ACTIVEn
+	 *	[42-43]	XG_MDC/XG_MDIO (XSMI)
+	 *	[44-55]	RGMII1
+	 *	[56-62]	SD
 	 */
-		/*   0    1    2    3    4    5    6    7    8    9 */
+	/*   0    1    2    3    4    5    6    7    8    9 */
 	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-		     0xff 0    7    0    7    0    0    2    2    0
-		     0    0    8    8    1    1    1    1    1    1
-		     1    1    1    1    1    1    0xe  0xe  0xe  0xe
-		     0xe  0xe  0xe >;
+		     0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
+		     0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
+		     0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
+		     0xe  0xe  0xe>;
+};
+
+&cpm_comphy {
+	/* Serdes Configuration:
+	 *	Lane 0: PCIe0 (x1)
+	 *	Lane 1: SATA0
+	 *	Lane 2: SFI (10G)
+	 *	Lane 3: SATA1
+	 *	Lane 4: USB3_HOST1
+	 *	Lane 5: PCIe2 (x1)
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <PHY_TYPE_SATA0>;
+	};
+	phy2 {
+		phy-type = <PHY_TYPE_SFI>;
+	};
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+	phy4 {
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+	};
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+	};
+};
+
+/* CON6 on CP0 expansion */
+&cpm_pcie0 {
+	status = "okay";
+};
+
+&cpm_pcie1 {
+	status = "disabled";
 };
 
 /* CON5 on CP0 expansion */
@@ -134,21 +174,69 @@
 	status = "okay";
 };
 
+&cpm_utmi0 {
+	status = "okay";
+};
+
+&cpm_utmi1 {
+	status = "okay";
+};
+
 &cps_pinctl {
 	/* MPP Bus:
-	 * [0-11]  RGMII0
-	 * [13-16] SPI1
-	 * [27,31] GE_MDIO/MDC
-	 * [32-62] = 0xff: Keep default CP1_shared_pins:
+	 *	[0-11]	RGMII0
+	 *	[13-16]	SPI1
+	 *	[27,31]	GE_MDIO/MDC
+	 *	[28]	SATA1_PRESENT_ACTIVEn
+	 *	[29-30]	UART0
+	 *	[32-62]	= 0xff: Keep default CP1_shared_pins
 	 */
-		/*   0    1    2    3    4    5    6    7    8    9 */
+	/*   0    1    2    3    4    5    6    7    8    9 */
 	pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
-		     0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
-		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
-		     0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+		     0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
+		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
+		     0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-		     0xff 0xff 0xff >;
+		     0xff 0xff 0xff>;
+};
+
+&cps_comphy {
+	/* Serdes Configuration:
+	 *	Lane 0: PCIe0 (x1)
+	 *	Lane 1: SATA0
+	 *	Lane 2: SFI (10G)
+	 *	Lane 3: SATA1
+	 *	Lane 4: PCIe1 (x1)
+	 *	Lane 5: PCIe2 (x1)
+	 */
+	phy0 {
+		phy-type = <PHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <PHY_TYPE_SATA0>;
+	};
+	phy2 {
+		phy-type = <PHY_TYPE_SFI>;
+	};
+	phy3 {
+		phy-type = <PHY_TYPE_SATA1>;
+	};
+	phy4 {
+		phy-type = <PHY_TYPE_PEX1>;
+	};
+	phy5 {
+		phy-type = <PHY_TYPE_PEX2>;
+	};
+};
+
+/* CON6 on CP1 expansion */
+&cps_pcie0 {
+	status = "okay";
+};
+
+&cps_pcie1 {
+	status = "okay";
 };
 
 /* CON5 on CP1 expansion */
@@ -200,86 +288,6 @@
 	status = "okay";
 };
 
-&cpm_comphy {
-	/*
-	 * Serdes Configuration:
-	 * Lane 0: SGMII2
-	 * Lane 1: USB3_HOST0
-	 * Lane 2: KR (10G)
-	 * Lane 3: SATA1
-	 * Lane 4: USB3_HOST1
-	 * Lane 5: PEX2x1
-	 */
-	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-	};
-
-	phy2 {
-		phy-type = <PHY_TYPE_KR>;
-	};
-
-	phy3 {
-		phy-type = <PHY_TYPE_SATA1>;
-	};
-
-	phy4 {
-		phy-type = <PHY_TYPE_USB3_HOST1>;
-	};
-
-	phy5 {
-		phy-type = <PHY_TYPE_PEX2>;
-	};
-};
-
-&cps_comphy {
-	/*
-	 * Serdes Configuration:
-	 * Lane 0: SGMII2
-	 * Lane 1: USB3_HOST0
-	 * Lane 2: KR (10G)
-	 * Lane 3: SATA1
-	 * Lane 4: Unconnected
-	 * Lane 5: PEX2x1
-	 */
-	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
-	};
-
-	phy1 {
-		phy-type = <PHY_TYPE_USB3_HOST0>;
-	};
-
-	phy2 {
-		phy-type = <PHY_TYPE_KR>;
-	};
-
-	phy3 {
-		phy-type = <PHY_TYPE_SATA1>;
-	};
-
-	phy4 {
-		phy-type = <PHY_TYPE_UNCONNECTED>;
-	};
-
-	phy5 {
-		phy-type = <PHY_TYPE_PEX2>;
-	};
-};
-
-&cpm_utmi0 {
-	status = "okay";
-};
-
-&cpm_utmi1 {
-	status = "okay";
-};
-
 &cps_utmi0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index e42b092b25..991ddc0c43 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -99,7 +99,7 @@
 	 * [54] 2.5G SFP LOS
 	 * [55] Micro SD card detect
 	 * [56-61] Micro SD
-	 * [62] CP1 KR SFP FAULT
+	 * [62] CP1 SFI SFP FAULT
 	 */
 		/*   0    1    2    3    4    5    6    7    8    9 */
 	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
@@ -163,7 +163,7 @@
 	 * Lane 1: PCIe0 (x4)
 	 * Lane 2: PCIe0 (x4)
 	 * Lane 3: PCIe0 (x4)
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SATA1
 	 */
 	phy0 {
@@ -179,7 +179,7 @@
 		phy-type = <PHY_TYPE_PEX0>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SATA1>;
@@ -264,15 +264,15 @@
 &cps_comphy {
 	/*
 	 * CP1 Serdes Configuration:
-	 * Lane 0: SGMII2
+	 * Lane 0: SGMII1
 	 * Lane 1: SATA 0
 	 * Lane 2: USB HOST 0
 	 * Lane 3: SATA1
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SGMII3
 	 */
 	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
+		phy-type = <PHY_TYPE_SGMII1>;
 		phy-speed = <PHY_SPEED_1_25G>;
 	};
 	phy1 {
@@ -285,7 +285,7 @@
 		phy-type = <PHY_TYPE_SATA1>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SGMII3>;
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 229046fba7..8c336f2c38 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -253,7 +253,7 @@
 				reg = <0x580000 0x1000>,	/* utmi-unit */
 				      <0x440420 0x4>,		/* usb-cfg */
 				      <0x440440 0x4>;		/* utmi-cfg */
-				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+				utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
 				status = "disabled";
 			};
 
@@ -262,7 +262,7 @@
 				reg = <0x581000 0x1000>,	/* utmi-unit */
 				      <0x440420 0x4>,		/* usb-cfg */
 				      <0x440444 0x4>;		/* utmi-cfg */
-				utmi-port = <UTMI_PHY_TO_USB_HOST1>;
+				utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
 				status = "disabled";
 			};
 
@@ -273,6 +273,20 @@
 				dma-coherent;
 				status = "disabled";
 			};
+
+			cpm_nand: nand@720000 {
+				compatible = "marvell,mvebu-pxa3xx-nand";
+				reg = <0x720000 0x100>;
+				#address-cells = <1>;
+
+				clocks = <&cpm_syscon0 1 2>;
+				nand-enable-arbiter;
+				num-cs = <1>;
+				nand-ecc-strength = <4>;
+				nand-ecc-step-size = <512>;
+				status = "disabled";
+			};
+
 		};
 
 		cpm_pcie0: pcie@f2600000 {
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
index 5876391449..0cdb3d3ae3 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -254,7 +254,7 @@
 				reg = <0x580000 0x1000>,	/* utmi-unit */
 				      <0x440420 0x4>,		/* usb-cfg */
 				      <0x440440 0x4>;		/* utmi-cfg */
-				utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+				utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index 2ef5726905..c2c176e3d4 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <libfdt.h>
+#include <pci.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/arch/cpu.h>
@@ -147,5 +148,10 @@ int arch_early_init_r(void)
 	/* Cause the SATA device to do its early init */
 	uclass_first_device(UCLASS_AHCI, &dev);
 
+#ifdef CONFIG_DM_PCI
+	/* Trigger PCIe devices detection */
+	pci_init();
+#endif
+
 	return 0;
 }
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 2325e9a180..38e7d33cb3 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -110,3 +110,21 @@ void reset_cpu(ulong ignored)
 	reg &= ~(1 << RFU_SW_RESET_OFFSET);
 	writel(reg, RFU_GLOBAL_SW_RST);
 }
+
+/*
+ * TODO - implement this functionality using platform
+ *        clock driver once it gets available
+ * Return NAND clock in Hz
+ */
+u32 mvebu_get_nand_clock(void)
+{
+	unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
+	unsigned long NF_CLOCK_SEL_MASK = 0x1;
+	u32 reg;
+
+	reg = readl(NAND_FLASH_CLK_CTRL);
+	if (reg & NF_CLOCK_SEL_MASK)
+		return 400 * 1000000;
+	else
+		return 250 * 1000000;
+}
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
index 104e7e88d7..0dfb9452e6 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
@@ -13,8 +13,6 @@
 #include "high_speed_env_spec.h"
 #include "sys_env_lib.h"
 
-#define SERDES_VERION	"2.0"
-
 u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
 	/* 0  1    2    3    4    5 */
 	{0x1, 0x1, NA,  NA,  NA,  NA},		/* PEX0 */
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index 820219e68e..883b90776a 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -27,7 +27,7 @@
  */
 struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
 
-#define	SERDES_VERION		"2.0"
+#define	SERDES_VERSION		"2.0"
 #define ENDED_OK		"High speed PHY - Ended Successfully\n"
 
 #define LINK_WAIT_CNTR		100
@@ -1416,7 +1416,7 @@ int serdes_phy_config(void)
 	DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
 
 	DEBUG_INIT_S("High speed PHY - Version: ");
-	DEBUG_INIT_S(SERDES_VERION);
+	DEBUG_INIT_S(SERDES_VERSION);
 	DEBUG_INIT_S("\n");
 
 	/* Init serdes sequences DB */
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index 5925bae69f..b0e193b78c 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -14,7 +14,7 @@
 #include "high_speed_env_spec.h"
 #include "board_env_spec.h"
 
-#define	SERDES_VERION	"2.1.5"
+#define	SERDES_VERSION	"2.1.5"
 #define ENDED_OK	"High speed PHY - Ended Successfully\n"
 
 static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
@@ -285,12 +285,12 @@ int serdes_phy_config(void)
 	if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 	    (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 		DEBUG_INIT_S("High speed PHY - Version: ");
-		DEBUG_INIT_S(SERDES_VERION);
+		DEBUG_INIT_S(SERDES_VERSION);
 		DEBUG_INIT_S(" - 2nd boot - Skip\n");
 		return MV_OK;
 	}
 	DEBUG_INIT_S("High speed PHY - Version: ");
-	DEBUG_INIT_S(SERDES_VERION);
+	DEBUG_INIT_S(SERDES_VERSION);
 	DEBUG_INIT_S(" (COM-PHY-V20)\n");
 
 	/*
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
index 115ec2cd60..704a59fa15 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <i2c.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>