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authorJagan Teki <jagan@amarulasolutions.com>2019-07-16 17:27:04 +0530
committerKever Yang <kever.yang@rock-chips.com>2019-07-20 23:59:44 +0800
commitb713e0291ba90847058678ae2752f08f238c8fe3 (patch)
tree06eb22e04409622afdeafc1403277a867dc4922f /arch/arm
parent01cc1039153d0ca4202e8b944e321637e27adc86 (diff)
ram: rk3399: Add ddr version enc macro
Add dram config macro for handling ddr version number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index f5c99fea8b..8027b53636 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -66,6 +66,7 @@ struct sdram_base_params {
* [1:0] dbw_ch0
*/
#define SYS_REG_DDRTYPE_SHIFT 13
+#define DDR_SYS_REG_VERSION 2
#define SYS_REG_DDRTYPE_MASK 7
#define SYS_REG_NUM_CH_SHIFT 12
#define SYS_REG_NUM_CH_MASK 1
@@ -99,6 +100,7 @@ struct sdram_base_params {
#define SYS_REG_DBW_MASK 3
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+#define SYS_REG_ENC_VERSION(n) ((n) << 28)
#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \