diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2018-06-05 15:18:32 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-06-15 08:06:31 +0200 |
| commit | bc0f4ed133e9996d00349b6b82ba65126fd70514 (patch) | |
| tree | fc656c64c140bbfd8ce1072725fa414f12551e02 /arch/arm | |
| parent | 0ecd14e63678ba0aa34a093cc73fe2c760eed142 (diff) | |
arm64: zynqmp: Split emmc configuration into emmc0 and emmc1
This patch splits the current mini emmc configuration into emmc0
and emmc1 configurations because emmc is probed at boot time and on
systems which have only one interface mini configuration is failing on
unused interface. This patch also adds required clock node in dts and
enables CONFIG_MMC_SDHCI_ZYNQ through defconfig.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-mini-emmc0.dts (renamed from arch/arm/dts/zynqmp-mini-emmc.dts) | 20 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-mini-emmc1.dts | 67 |
3 files changed, 75 insertions, 15 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 078c21b401..493652ea8c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,7 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-mini-emmc.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index e5b3c5fc78..24dd1ab9df 100644 --- a/arch/arm/dts/zynqmp-mini-emmc.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -18,7 +18,6 @@ aliases { serial0 = &dcc; mmc0 = &sdhci0; - mmc1 = &sdhci1; }; chosen { @@ -36,6 +35,12 @@ u-boot,dm-pre-reloc; }; + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + amba: amba { compatible = "simple-bus"; #address-cells = <2>; @@ -50,15 +55,6 @@ clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; }; - - sdhci1: sdhci@ff170000 { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <1>; - }; }; }; @@ -69,7 +65,3 @@ &sdhci0 { status = "okay"; }; - -&sdhci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts new file mode 100644 index 0000000000..d1549b6dc6 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI EMMC"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff170000 0x0 0x1000>; + clock-names = "clk_xin", "clk_xin"; + xlnx,device_id = <1>; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; |