diff options
| author | David Wu <david.wu@rock-chips.com> | 2018-01-13 14:06:16 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2018-01-28 17:12:38 +0100 |
| commit | c513e9e1e6e1ea2aa177aae3b0eb306c949dcd69 (patch) | |
| tree | 6585ee3f0750f32041d5b59f7bf7bd5886ce047a /arch/arm | |
| parent | a50e5c9e333832b4c26820c229fa0fe5688fed29 (diff) | |
ARM: dts: rk3288: Remove unused LCDC clock assigned
The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/rk3288.dtsi | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index da518783e2..2c8a616782 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -604,19 +604,16 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_NPLL>, <&cru ACLK_CPU>, <&cru HCLK_CPU>, <&cru PCLK_CPU>, <&cru ACLK_PERI>, <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <0>, <0>, - <594000000>, <400000000>, + assigned-clock-rates = <594000000>, <400000000>, <500000000>, <300000000>, <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; - assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; }; grf: syscon@ff770000 { |