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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-11 20:17:49 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-25 00:27:53 +0900
commitcf88affab6c46bc728d47fe2590c465734d78efb (patch)
tree24918bad7814f9a9877ed7033091d9b8ee154e3c /arch/arm
parent9628afa7f5cd6d752adc7bb77ea14fd639a66d03 (diff)
ARM: uniphier: parse device tree to determine DRAM base and size
Device tree specifies the available memory ranges in its "/memory" node. Use it to simplify the CONFIG defines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-uniphier/board_common.c12
-rw-r--r--arch/arm/mach-uniphier/dram_init.c51
2 files changed, 47 insertions, 16 deletions
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
index 5f2d5f6f5b..967fa6c086 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -18,15 +18,3 @@ int board_init(void)
return 0;
}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
- gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
-}
-#endif
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index 4b8c938b5e..32cc448aeb 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -1,16 +1,59 @@
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/memory");
+ if (offset < 0)
+ return NULL;
+
+ return fdt_getprop(fdt, offset, "reg", lenp);
+}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ const fdt32_t *val;
+ int len;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < sizeof(*val))
+ return -EINVAL;
+
+ gd->ram_size = fdt32_to_cpu(*(val + 1));
+
+ debug("DRAM size = %08lx\n", gd->ram_size);
return 0;
}
+
+void dram_init_banksize(void)
+{
+ const fdt32_t *val;
+ int len, i;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < 0)
+ return;
+
+ len /= sizeof(*val);
+ len /= 2;
+
+ for (i = 0; i < len; i++) {
+ gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
+ gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+
+ debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ }
+}