diff options
| author | Ajay Bhargav <[ajay.bhargav@einfochips.com]> | 2011-10-03 14:00:57 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:32 +0200 |
| commit | daa4b2f7f5e023dffa272e86b0f271b07f9813b8 (patch) | |
| tree | d360aef6981ae9c8a1059c1e7ff966470085dc9f /arch/arm | |
| parent | 51100cfccac710367249515f685f1a33c95cceb4 (diff) | |
Armada100: Add SPI support for Marvell gplugD
This patch add SPI driver support for Marvell gplugD
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/armada100.h | 19 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/mfp.h | 6 |
2 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index c449d4e639..a8181b68db 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -45,6 +45,10 @@ #define FE_CLK_RST 0x1 #define FE_CLK_ENA 0x8 +/* SSP2 Clock Control */ +#define SSP2_APBCLK 0x01 +#define SSP2_FNCLK 0x02 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_FEC_BASE 0xC0800000 @@ -175,5 +179,20 @@ struct armd1apb1_registers { u32 ac97; /*0x084*/ }; +/* +* APB2 Clock Reset/Control Registers +* Refer Datasheet Appendix A.11 +*/ +struct armd1apb2_registers { + u32 pad1[0x01C - 0x000]; + u32 ssp1_clkrst; /* 0x01C */ + u32 ssp2_clkrst; /* 0x020 */ + u32 pad2[0x04C - 0x020 - 4]; + u32 ssp3_clkrst; /* 0x04C */ + u32 pad3[0x058 - 0x04C - 4]; + u32 ssp4_clkrst; /* 0x058 */ + u32 ssp5_clkrst; /* 0x05C */ +}; + #endif /* CONFIG_ARMADA100 */ #endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index da76b58405..d48251af20 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -83,6 +83,12 @@ #define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) #define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +/* SPI */ +#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 |