ARM: tegra: pinctrl: remove vddio

This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

8 files changed, 0 insertions, 86 deletions

diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 7bf494c49a..e83a29f43a 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -24,7 +24,6 @@
 struct tegra_pingroup_desc {
 	const char *name;
 	enum pmux_func funcs[4];
-	enum pmux_vddio vddio;
 	enum pmux_pin_io io;
 };
 
@@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
 	{						\
-		.vddio = PMUX_VDDIO_ ## vdd,		\
 		.funcs = {				\
 			PMUX_FUNC_ ## f0,		\
 			PMUX_FUNC_ ## f1,		\
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
index b1ac59e5b3..921dd2119b 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -15,7 +15,6 @@
 struct tegra_pingroup_desc {
 	const char *name;
 	enum pmux_func funcs[4];
-	enum pmux_vddio vddio;
 	enum pmux_pin_io io;
 };
 
@@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
 	{						\
-		.vddio = PMUX_VDDIO_ ## vdd,		\
 		.funcs = {				\
 			PMUX_FUNC_ ## f0,		\
 			PMUX_FUNC_ ## f1,		\
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
index 1f04d9c7ff..40301e13c2 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -259,7 +259,6 @@ enum pmux_pullid {
 struct tegra_pingroup_desc {
 	const char *name;
 	enum pmux_func funcs[4];
-	enum pmux_vddio vddio;
 	enum pmux_ctlid ctl_id;
 	enum pmux_pullid pull_id;
 };
@@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd)		\
 	{						\
-		.vddio = PMUX_VDDIO_ ## vdd,		\
 		.funcs = {				\
 			PMUX_FUNC_ ## f0,			\
 			PMUX_FUNC_ ## f1,			\
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 6fd424981c..8eca0dd654 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -24,7 +24,6 @@
 struct tegra_pingroup_desc {
 	const char *name;
 	enum pmux_func funcs[4];
-	enum pmux_vddio vddio;
 	enum pmux_pin_io io;
 };
 
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
 	{						\
-		.vddio = PMUX_VDDIO_ ## vdd,		\
 		.funcs = {				\
 			PMUX_FUNC_ ## f0,		\
 			PMUX_FUNC_ ## f1,		\
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index edf1a89ce1..93d2ca525c 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
 				(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
 				((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-	PMUX_VDDIO_BB = 0,
-	PMUX_VDDIO_LCD,
-	PMUX_VDDIO_VI,
-	PMUX_VDDIO_UART,
-	PMUX_VDDIO_DDR,
-	PMUX_VDDIO_NAND,
-	PMUX_VDDIO_SYS,
-	PMUX_VDDIO_AUDIO,
-	PMUX_VDDIO_SD,
-	PMUX_VDDIO_CAM,
-	PMUX_VDDIO_GMI,
-	PMUX_VDDIO_PEXCTL,
-	PMUX_VDDIO_SDMMC1,
-	PMUX_VDDIO_SDMMC3,
-	PMUX_VDDIO_SDMMC4,
-
-	PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE	-1
 #define PGRP_SLWF_MAX	3
 #define PGRP_SLWR_NONE	PGRP_SLWF_NONE
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index f51f44a54a..2042f1f7e5 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -458,27 +458,6 @@ enum pmux_pin_rcv_sel {
 				(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
 				((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-	PMUX_VDDIO_BB = 0,
-	PMUX_VDDIO_LCD,
-	PMUX_VDDIO_VI,
-	PMUX_VDDIO_UART,
-	PMUX_VDDIO_DDR,
-	PMUX_VDDIO_NAND,
-	PMUX_VDDIO_SYS,
-	PMUX_VDDIO_AUDIO,
-	PMUX_VDDIO_SD,
-	PMUX_VDDIO_CAM,
-	PMUX_VDDIO_GMI,
-	PMUX_VDDIO_PEXCTL,
-	PMUX_VDDIO_SDMMC1,
-	PMUX_VDDIO_SDMMC3,
-	PMUX_VDDIO_SDMMC4,
-
-	PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE	-1
 #define PGRP_SLWF_MAX	3
 #define PGRP_SLWR_NONE	PGRP_SLWF_NONE
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 3374d9c40f..2bfaf53d34 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -257,21 +257,6 @@ enum pmux_tristate {
 	PMUX_TRI_TRISTATE = 1,
 };
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-	PMUX_VDDIO_BB = 0,
-	PMUX_VDDIO_LCD,
-	PMUX_VDDIO_VI,
-	PMUX_VDDIO_UART,
-	PMUX_VDDIO_DDR,
-	PMUX_VDDIO_NAND,
-	PMUX_VDDIO_SYS,
-	PMUX_VDDIO_AUDIO,
-	PMUX_VDDIO_SD,
-
-	PMUX_VDDIO_NONE
-};
-
 enum {
 	PMUX_TRISTATE_REGS	= 4,
 	PMUX_MUX_REGS		= 7,
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index ff2511e877..0704e4d4d4 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -509,27 +509,6 @@ enum pmux_pin_ioreset {
 				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
 				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-	PMUX_VDDIO_BB = 0,
-	PMUX_VDDIO_LCD,
-	PMUX_VDDIO_VI,
-	PMUX_VDDIO_UART,
-	PMUX_VDDIO_DDR,
-	PMUX_VDDIO_NAND,
-	PMUX_VDDIO_SYS,
-	PMUX_VDDIO_AUDIO,
-	PMUX_VDDIO_SD,
-	PMUX_VDDIO_CAM,
-	PMUX_VDDIO_GMI,
-	PMUX_VDDIO_PEXCTL,
-	PMUX_VDDIO_SDMMC1,
-	PMUX_VDDIO_SDMMC3,
-	PMUX_VDDIO_SDMMC4,
-
-	PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE	-1
 #define PGRP_SLWF_MAX	3
 #define	PGRP_SLWR_NONE	PGRP_SLWF_NONE