diff options
| author | Marek Vasut <marex@denx.de> | 2015-12-20 04:00:41 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-12-22 21:30:02 +0100 |
| commit | f2f3782eadc7a958b0d33e9746640b874b5eefcc (patch) | |
| tree | f050774688bd94a634542be1d5f7d56df0ec491e /arch/arm | |
| parent | caee45ecc32329294d0f42a54b5c47794ecbe750 (diff) | |
arm: socfpga: Define NAND reset bit
Define the NAND reset bit and fix the ordering of the macros.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd86e6..2f070f291c 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) |