diff options
| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2017-01-30 12:06:02 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-11-28 16:09:09 +0100 |
| commit | f811eca9db05fc89fe52141b256231ff94859add (patch) | |
| tree | b5be64c6e74426bddbeb5ba48705dee42846f7b9 /arch/arm | |
| parent | d801ce553e84fded21060804f577b944da445317 (diff) | |
arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/zynqmp-zcu102-revA.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index fd7d646671..df916d0f77 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -168,7 +168,7 @@ gtr_sel0 { gpio-hog; gpios = <0 0>; - output-high; /* PCIE = 0, DP = 1 */ + output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { @@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o }; &pcie { -/* status = "okay"; */ + status = "okay"; }; &qspi { |