Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver

12 files changed, 299 insertions, 40 deletions

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 5ac48ebc4d..5ffc9f6c86 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -56,6 +56,17 @@ config ZYNQMP_USB
 config SYS_MALLOC_F_LEN
 	default 0x600
 
+config DEFINE_TCM_OCM_MMAP
+	bool "Define TCM and OCM memory in MMU Table"
+	help
+	  This option if enabled defines the TCM and OCM memory and its
+	  memory attributes in MMU table entry.
+
+config ZYNQMP_PSU_INIT_ENABLED
+	bool "Include psu_init"
+	help
+	  Include psu_init to full u-boot. SPL include psu_init by default.
+
 config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
 	bool "Overwrite SPL bootmode"
 	depends on SPL
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 94ecf90660..1b5066a826 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -38,6 +38,14 @@ static struct mm_region zynqmp_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+		.virt = 0xffe00000UL,
+		.phys = 0xffe00000UL,
+		.size = 0x00200000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+#endif
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
 		.size = 0x200000000UL,
@@ -102,9 +110,8 @@ unsigned int zynqmp_get_silicon_version(void)
 #define ZYNQMP_MMIO_READ	0xC2000014
 #define ZYNQMP_MMIO_WRITE	0xC2000013
 
-#ifndef CONFIG_SPL_BUILD
-int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
-	       u32 *ret_payload)
+int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
+			      u32 arg3, u32 *ret_payload)
 {
 	/*
 	 * Added SIP service call Function Identifier
@@ -164,28 +171,7 @@ void zynqmp_pmufw_version(void)
 }
 #endif
 
-int zynqmp_mmio_write(const u32 address,
-		      const u32 mask,
-		      const u32 value)
-{
-	return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
-}
-
-int zynqmp_mmio_read(const u32 address, u32 *value)
-{
-	u32 ret_payload[PAYLOAD_ARG_CNT];
-	u32 ret;
-
-	if (!value)
-		return -EINVAL;
-
-	ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
-	*value = ret_payload[1];
-
-	return ret;
-}
-#else
-int zynqmp_mmio_write(const u32 address,
+static int zynqmp_mmio_rawwrite(const u32 address,
 		      const u32 mask,
 		      const u32 value)
 {
@@ -200,9 +186,40 @@ int zynqmp_mmio_write(const u32 address,
 	return 0;
 }
 
-int zynqmp_mmio_read(const u32 address, u32 *value)
+static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 {
 	*value = readl((ulong)address);
 	return 0;
 }
-#endif
+
+int zynqmp_mmio_write(const u32 address,
+		      const u32 mask,
+		      const u32 value)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
+		return zynqmp_mmio_rawwrite(address, mask, value);
+	else if (!IS_ENABLED(CONFIG_SPL_BUILD))
+		return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
+				  value, 0, NULL);
+
+	return -EINVAL;
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 ret;
+
+	if (!value)
+		return -EINVAL;
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+		ret = zynqmp_mmio_rawread(address, value);
+	} else if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+		ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
+				 0, ret_payload);
+		*value = ret_payload[1];
+	}
+
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index e10fc3136c..76f889ba7d 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -206,6 +206,21 @@ static void write_tcm_boot_trampoline(u32 boot_addr)
 	}
 }
 
+void initialize_tcm(bool mode)
+{
+	if (!mode) {
+		set_r5_tcm_mode(LOCK);
+		set_r5_halt_mode(HALT, LOCK);
+		enable_clock_r5();
+		release_r5_reset(LOCK);
+	} else {
+		set_r5_tcm_mode(SPLIT);
+		set_r5_halt_mode(HALT, SPLIT);
+		enable_clock_r5();
+		release_r5_reset(SPLIT);
+	}
+}
+
 int cpu_release(int nr, int argc, char * const argv[])
 {
 	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 26bf80ec52..468dc1dc4d 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -17,7 +17,7 @@
 
 void board_init_f(ulong dummy)
 {
-	psu_init();
+	board_early_init_f();
 	board_early_init_r();
 
 #ifdef CONFIG_DEBUG_UART
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 422b88bc9a..708709382c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -132,13 +132,14 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-topic-miami.dtb \
 	zynq-topic-miamilite.dtb \
 	zynq-topic-miamiplus.dtb \
+	zynq-zturn-myir.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-ep108.dtb			\
-	zynqmp-zcu102.dtb			\
+	zynqmp-zcu102-revA.dtb			\
 	zynqmp-zcu102-revB.dtb			\
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 34fc6e5f89..f993e19ef2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -38,6 +38,14 @@
 		};
 	};
 
+	fpga_full: fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <&devcfg>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
 	pmu@f8891000 {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 5 4>, <0 6 4>;
diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn-myir.dts
new file mode 100644
index 0000000000..a5ecfcc1d7
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-myir.dts
@@ -0,0 +1,161 @@
+/*
+ *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
+ *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
+ *
+ *  Based on zynq-zed.dts which is:
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq Z-Turn MYIR Board";
+	compatible = "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		led_r {
+			label = "led_r";
+			gpios = <&gpio0 0x72 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_g {
+			label = "led_g";
+			gpios = <&gpio0 0x73 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_b {
+			label = "led_b";
+			gpios = <&gpio0 0x74 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		usr_led1 {
+			label = "usr_led1";
+			gpios = <&gpio0 0x0 0x1>;
+			default-state = "off";
+			linux,default-trigger = "none";
+		};
+
+		usr_led2 {
+			label = "usr_led2";
+			gpios = <&gpio0 0x9 0x1>;
+			default-state = "off";
+			linux,default-trigger = "none";
+		};
+	};
+
+	gpio-beep {
+		compatible = "gpio-beeper";
+		label = "pl-beep";
+		gpios = <&gpio0 0x75 0x0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		autorepeat;
+		K1 {
+			label = "K1";
+			gpios = <&gpio0 0x32 0x1>;
+			linux,code = <0x66>;
+			gpio-key,wakeup;
+			autorepeat;
+		};
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+	fclk-enable = <0xf>;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	stlm75@49 {
+		status = "okay";
+		compatible = "lm75";
+		reg = <0x49>;
+	};
+
+	adxl345@53 {
+		compatible = "adi,adxl34x", "adxl34x";
+		reg = <0x53>;
+		interrupt-parent = <&intc>;
+		interrupts = <0x0 0x1e 0x4>;
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 0e9150e6b1..d8ac008f2b 100644
--- a/arch/arm/dts/zynqmp-zcu102.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -16,7 +16,7 @@
 
 / {
 	model = "ZynqMP ZCU102 RevA";
-	compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
 
 	aliases {
 		ethernet0 = &gem3;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 765108e437..82337332f9 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -8,7 +8,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "zynqmp-zcu102.dts"
+#include "zynqmp-zcu102-revA.dts"
 
 / {
 	model = "ZynqMP ZCU102 RevB";
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index cf187f3111..cab29ba036 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -48,18 +48,9 @@ struct crlapb_regs {
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
 
 #define ZYNQMP_IOU_SCNTR_SECURE	0xFF260000
-#define ZYNQMP_IOU_SCNTR	0xFF250000
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
 
-struct iou_scntr {
-	u32 counter_control_register;
-	u32 reserved0[7];
-	u32 base_frequency_id_register;
-};
-
-#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
-
 struct iou_scntr_secure {
 	u32 counter_control_register;
 	u32 reserved0[7];
@@ -153,4 +144,7 @@ struct pmu_regs {
 
 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
 
+#define ZYNQMP_CSU_IDCODE_ADDR	0xFFCA0040
+#define ZYNQMP_CSU_VER_ADDR	0xFFCA0044
+
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index d91d98a119..e52abd71a5 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -10,6 +10,25 @@
 
 #define PAYLOAD_ARG_CNT		5
 
+#define ZYNQMP_CSU_SILICON_VER_MASK	0xF
+
+enum {
+	IDCODE,
+	VERSION,
+};
+
+enum {
+	ZYNQMP_SILICON_V1,
+	ZYNQMP_SILICON_V2,
+	ZYNQMP_SILICON_V3,
+	ZYNQMP_SILICON_V4,
+};
+
+enum {
+	TCM_LOCK,
+	TCM_SPLIT,
+};
+
 int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);
@@ -24,4 +43,8 @@ int zynqmp_mmio_read(const u32 address, u32 *value);
 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
 	       u32 *ret_payload);
 
+void initialize_tcm(bool mode);
+
+int chip_id(unsigned char id);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 4dc9bb0102..86559cb6aa 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -42,6 +42,35 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
 	.image_copy_end :
 	{
 		*(.__image_copy_end)