diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2018-05-07 13:03:24 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-05-28 16:40:43 +0530 |
| commit | fef73766d9ad4ca76b47faf6436f096ec40b3e7c (patch) | |
| tree | de386101ba3371ff196d9410e350fe750e3090c4 /arch/arm | |
| parent | 5c5fe883e046008ab311614ef02f87c551c30535 (diff) | |
sunxi: clock: Fix OHCI clock gating for H3/H5
Clock gating bits on H43/H5 were wrong, fix them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 87d82f205c..8acf79fbba 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -350,13 +350,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) |