diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2013-04-11 17:42:38 +0800 |
|---|---|---|
| committer | Sonic Zhang <sonic.zhang@analog.com> | 2013-05-13 16:30:26 +0800 |
| commit | 85f2f8f9adb13535cefcbd4987d2e8e5a978ccd4 (patch) | |
| tree | 3488458f9ddfda86a5afcd61060acaeafb7c52f0 /arch/blackfin/cpu/initcode.c | |
| parent | 9d803fc8125a3528f700da9064d1bfa3fbc56b13 (diff) | |
blackfin: Add comments for watchdog event initialization.
- Add comments for watchdog event initialization.
- Make sure the writting operation to MMRs are finished.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Diffstat (limited to 'arch/blackfin/cpu/initcode.c')
| -rw-r--r-- | arch/blackfin/cpu/initcode.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 5fc06e11ff..ffaf1017d7 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -458,15 +458,23 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { serial_putc('e'); #ifdef __ADSPBF60x__ + /* Reset system event controller */ bfin_write_SEC_GCTL(0x2); + bfin_write_SEC_CCTL(0x2); SSYNC(); + + /* Enable fault event input and system reset action in fault + * controller. Route watchdog timeout event to fault interface. + */ bfin_write_SEC_FCTL(0xc1); + /* Enable watchdog interrupt source */ bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6); - - bfin_write_SEC_CCTL(0x2); SSYNC(); + + /* Enable system event controller */ bfin_write_SEC_GCTL(0x1); bfin_write_SEC_CCTL(0x1); + SSYNC(); #endif bfin_write_WDOG_CTL(WDDIS); SSYNC(); |