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authorTom Rini <trini@ti.com>2013-03-11 12:02:40 -0400
committerTom Rini <trini@ti.com>2013-03-11 12:16:13 -0400
commit76b40ab41eff1f402ee52ba768b09daad293b9bb (patch)
tree4956296adbdc8939aa49d84fa9bd497eef65b7f4 /arch/blackfin/include/asm/mach-common/bits/pll.h
parentde62688bb61c499ecc2d70a3aa8ccf90bb7a8ef6 (diff)
parentfc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4 (diff)
Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/blackfin/include/asm/mach-common/bits/pll.h')
-rw-r--r--arch/blackfin/include/asm/mach-common/bits/pll.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
index 9009f26401..fe0ba0f543 100644
--- a/arch/blackfin/include/asm/mach-common/bits/pll.h
+++ b/arch/blackfin/include/asm/mach-common/bits/pll.h
@@ -16,6 +16,8 @@
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
+#define MSEL_P 9
+
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
@@ -29,6 +31,9 @@
#define CCLK_DIV4 CSEL_DIV4
#define CCLK_DIV8 CSEL_DIV8
+#define SSEL_P 0
+#define CSEL_P 4
+
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */