diff options
| author | Angelo Dureghello <angelo@sysam.it> | 2018-01-25 22:42:52 +0100 |
|---|---|---|
| committer | Angelo Dureghello <angelo@sysam.it> | 2018-09-16 00:01:13 +0200 |
| commit | 2c92e4fbc69841170939a48e887c8fbbcb23d05c (patch) | |
| tree | 964abbd17b80450d8ce4eda3192c30474f6ce638 /arch/m68k/cpu/mcf5445x | |
| parent | faae49543a0b366087cb733c26f8c581b17abe82 (diff) | |
m68k: ColdFire mcf5441x, add eSDHC support
This patch adds mcf5441x eSDHC support for the mcf5441x family.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Diffstat (limited to 'arch/m68k/cpu/mcf5445x')
| -rw-r--r-- | arch/m68k/cpu/mcf5445x/cpu_init.c | 10 | ||||
| -rw-r--r-- | arch/m68k/cpu/mcf5445x/speed.c | 2 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 0b86020204..7632d9262c 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -173,6 +173,15 @@ void cpu_init_f(void) /* Lowest slew rate for UART0,1,2 */ out_8(&gpio->srcr_uart, 0x00); + +#ifdef CONFIG_FSL_ESDHC + /* eSDHC pin as faster speed */ + out_8(&gpio->srcr_sdhc, 0x03); + + /* All esdhc pins as SD */ + out_8(&gpio->par_sdhch, 0xff); + out_8(&gpio->par_sdhcl, 0xff); +#endif #endif /* CONFIG_MCF5441x */ #ifdef CONFIG_MCF5445x @@ -534,4 +543,5 @@ void cfspi_release_bus(uint bus, uint cs) clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); #endif } + #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 5214730a0f..e15e32ebde 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -120,6 +120,8 @@ void setup_5441x_clocks(void) temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; gd->bus_clk = vco / temp; /* bus clock */ + temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1; + gd->arch.sdhc_clk = vco / temp; } #endif |