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| author | Michal Simek <michal.simek@xilinx.com> | 2014-01-21 07:30:37 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-04 16:39:50 +0100 |
| commit | 9d24274509cdd463992dc1fb1a2820d6a4b6d21d (patch) | |
| tree | aa599f1c017ae0a597daf3394e8a45ed3192396d /arch/microblaze/cpu/start.S | |
| parent | 22ff7f4d195b49ca7db5b2a0c3aa2c987ab88c34 (diff) | |
microblaze: Add SPL support
Add support for U-BOOT SPL. NOR and RAM mode are supported.
There are 3 images in NOR flash. u-boot.img, dtb and kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze/cpu/start.S')
| -rw-r--r-- | arch/microblaze/cpu/start.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8928024838..1757bbfa94 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -22,6 +22,11 @@ _start: */ mts rmsr, r0 /* disable cache */ + +#if defined(CONFIG_SPL_BUILD) + addi r1, r0, CONFIG_SPL_STACK_ADDR + addi r1, r1, -4 /* Decrement SP to top of memory */ +#else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ @@ -115,6 +120,7 @@ _start: sh r7, r0, r8 rsubi r8, r10, 0x26 sh r6, r0, r8 +#endif /* BUILD_SPL */ /* Flush cache before enable cache */ addik r5, r0, 0 @@ -139,9 +145,14 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifndef CONFIG_SPL_BUILD brai board_init_f +#else + brai board_init_r +#endif 1: bri 1b +#ifndef CONFIG_SPL_BUILD /* * Read 16bit little endian */ @@ -174,3 +185,4 @@ out16: bslli r3, r6, 8 rtsd r15, 8 or r0, r0, r0 .end out16 +#endif |