diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2015-01-29 01:28:02 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2015-01-29 12:55:01 +0100 |
| commit | dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e (patch) | |
| tree | a2db8dc572e96427919f6f1bae496c3abff8cd5e /arch/mips/Kconfig | |
| parent | ca4e833cd6409c72e5b13ee803a4f08381e6d160 (diff) | |
MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ef7892975a..bc4283d2f1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -36,6 +36,7 @@ config TARGET_VCT select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD config TARGET_DBAU1X00 bool "Support dbau1x00" @@ -43,12 +44,14 @@ config TARGET_DBAU1X00 select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD config TARGET_PB1X00 bool "Support pb1x00" select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD endchoice @@ -185,6 +188,9 @@ config 64BIT config SWAP_IO_SPACE bool +config SYS_MIPS_CACHE_INIT_RAM_LOAD + bool + endif endmenu |