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authorJens Kuske <jenskuske@gmail.com>2016-08-19 13:40:46 +0200
committerHans de Goede <hdegoede@redhat.com>2016-08-26 16:58:37 +0200
commitd5ac6eef91965b519d8f15f17febfa0ea2ee0adc (patch)
treecba94fb97afcef4df858fc6d136fd2a0b4b8a2e4 /arch/mips/cpu/cpu.c
parent421c98d7d2ebf929debf907e75ec04419cf07dbe (diff)
sunxi: Tune H3 DRAM PLL to improve lock time
The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/mips/cpu/cpu.c')
0 files changed, 0 insertions, 0 deletions