diff options
| author | Tom Rini <trini@ti.com> | 2012-10-17 08:57:13 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-17 08:57:13 -0700 |
| commit | d1ff690612415470a681787c029803952142043d (patch) | |
| tree | 09a7a42be56797aa57abefc8f464bffa1ecb16da /arch/mips/cpu/mips32/cpu.c | |
| parent | ff04f6d1224d8952b566b8671222151495883073 (diff) | |
| parent | 6b2eba1b7cd661fc6b2b0e0d4d039d1c299e2e07 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch/mips/cpu/mips32/cpu.c')
| -rw-r--r-- | arch/mips/cpu/mips32/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 7b49e1b612..50bb248bd0 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size) return; while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); if (addr == aend) break; addr += lsize; @@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Writeback_Inv_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); if (addr == aend) break; addr += lsize; @@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Invalidate_D, addr); + cache_op(HIT_INVALIDATE_D, addr); if (addr == aend) break; addr += lsize; |