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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-02-12 22:22:12 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-02-12 22:22:12 +0100 |
| commit | 8b1c7345c6d5ed20b6b5ec8db17a3282e592184d (patch) | |
| tree | 33936d45ff2e416129a1bf5e8d25da4ac4ab8e6b /arch/mips/cpu/mips64/start.S | |
| parent | 4dc7412afa4fe47a02805525e415656d67764839 (diff) | |
MIPS: start.S: unify and simplify reset vector handling
Adopt reset vector handling from Yamon.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/cpu/mips64/start.S')
| -rw-r--r-- | arch/mips/cpu/mips64/start.S | 47 |
1 files changed, 21 insertions, 26 deletions
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 15225945e9..c0ae41a18a 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -52,40 +52,40 @@ .globl _start .text _start: - .org 0x000 + /* U-boot entry point */ b reset nop - .org 0x080 - b romReserved - nop - .org 0x100 - b romReserved - nop - .org 0x180 - b romReserved - nop + .org 0x200 - b romReserved + /* TLB refill, 32 bit task */ +1: b 1b nop + .org 0x280 - b romReserved + /* XTLB refill, 64 bit task */ +1: b 1b nop + .org 0x300 - b romReserved + /* Cache error exception */ +1: b 1b nop + .org 0x380 - b romReserved + /* General exception */ +1: b 1b nop + + .org 0x400 + /* Catch interrupt exceptions */ +1: b 1b + nop + .org 0x480 - b romReserved + /* EJTAG debug exception */ +1: b 1b nop - /* - * We hope there are no more reserved vectors! - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ - .org 0x500 .align 4 reset: @@ -238,8 +238,3 @@ in_ram: move a1, s2 .end relocate_code - - /* Exception handlers */ -romReserved: - b romReserved - nop |