diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:51 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | f8981277f581564bf701d310fe0f68903cf3f542 (patch) | |
| tree | b21d2134c34a7bfe6bcce532d4872353569ab2eb /arch/mips/cpu/start.S | |
| parent | 4f9226b40379847339af8a7777be26f2db72e79b (diff) | |
MIPS: If we don't need DDR for cache init, init cache first
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/cpu/start.S')
| -rw-r--r-- | arch/mips/cpu/start.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6aec430a67..6f1d2192b0 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -142,15 +142,24 @@ reset: PTR_L gp, 0(ra) #ifndef CONFIG_SKIP_LOWLEVEL_INIT +# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ PTR_LA t9, lowlevel_init jalr t9 nop +# endif /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalr t9 nop + +# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init + jalr t9 + nop +# endif #endif /* Set up temporary stack */ |