diff options
| author | Tom Rini <trini@ti.com> | 2012-10-17 08:57:13 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-17 08:57:13 -0700 |
| commit | d1ff690612415470a681787c029803952142043d (patch) | |
| tree | 09a7a42be56797aa57abefc8f464bffa1ecb16da /arch/mips/cpu/xburst | |
| parent | ff04f6d1224d8952b566b8671222151495883073 (diff) | |
| parent | 6b2eba1b7cd661fc6b2b0e0d4d039d1c299e2e07 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch/mips/cpu/xburst')
| -rw-r--r-- | arch/mips/cpu/xburst/cpu.c | 12 | ||||
| -rw-r--r-- | arch/mips/cpu/xburst/start.S | 4 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index ddcbfaa47c..cc190dfe56 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size) unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); } } @@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) - cache_op(Hit_Writeback_Inv_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } void invalidate_dcache_range(ulong start_addr, ulong stop) @@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) - cache_op(Hit_Invalidate_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } void flush_icache_all(void) @@ -118,7 +118,7 @@ void flush_icache_all(void) for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(Index_Store_Tag_I, addr); + cache_op(INDEX_STORE_TAG_I, addr); } /* invalidate btb */ @@ -139,7 +139,7 @@ void flush_dcache_all(void) for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(Index_Writeback_Inv_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } __asm__ __volatile__("sync"); diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index d846104d10..3a8280cb0a 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -96,7 +96,7 @@ relocate_code: li t0, KSEG0 addi t1, t0, CONFIG_SYS_DCACHE_SIZE 2: - cache Index_Writeback_Inv_D, 0(t0) + cache INDEX_WRITEBACK_INV_D, 0(t0) bne t0, t1, 2b addi t0, CONFIG_SYS_CACHELINE_SIZE @@ -106,7 +106,7 @@ relocate_code: li t0, KSEG0 addi t1, t0, CONFIG_SYS_ICACHE_SIZE 3: - cache Index_Invalidate_I, 0(t0) + cache INDEX_INVALIDATE_I, 0(t0) bne t0, t1, 3b addi t0, CONFIG_SYS_CACHELINE_SIZE |