Merge branch 'master' of git://git.denx.de/u-boot-mips

4 files changed, 64 insertions, 112 deletions

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 384ea26022..36b92cc687 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -15,6 +15,11 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
 	/*
 	 * For the moment disable interrupts, mark the kernel mode and
 	 * set ST0_KX so that the CPU does not spit fire when using
@@ -135,9 +140,31 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	li	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+	li	t0, -16
+	li	t1, CONFIG_SYS_INIT_SP_ADDR
+	and	sp, t1, t0		# force 16 byte alignment
+	sub	sp, sp, GD_SIZE		# reserve space for gd
+	and	sp, sp, t0		# force 16 byte alignment
+	move	k0, sp			# save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	li	t2, CONFIG_SYS_MALLOC_F_LEN
+	sub	sp, sp, t2		# reserve space for early malloc
+	and	sp, sp, t0		# force 16 byte alignment
+#endif
 	move	fp, sp
 
+	/* Clear gd */
+	move	t0, k0
+1:
+	sw	zero, 0(t0)
+	blt	t0, t1, 1b
+	 addi	t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	addu	t0, k0, GD_MALLOC_BASE	# gd->malloc_base offset
+	sw	sp, 0(t0)
+#endif
+
 	la	t9, board_init_f
 	jr	t9
 	 move	ra, zero
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c
index 386f45a1b0..553da5f4ba 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/mips32/time.c
@@ -8,63 +8,12 @@
 #include <common.h>
 #include <asm/mipsregs.h>
 
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	\
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
+unsigned long notrace timer_read_counter(void)
 {
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
+	return read_c0_count();
 }
 
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+ulong notrace get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return CONFIG_SYS_MIPS_TIMER_FREQ;
 }
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 6ff714e8ed..471bc1eb66 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -15,6 +15,11 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
 #ifdef CONFIG_SYS_LITTLE_ENDIAN
 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
 	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
@@ -129,9 +134,31 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	dli	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+	dli	t0, -16
+	dli	t1, CONFIG_SYS_INIT_SP_ADDR
+	and	sp, t1, t0		# force 16 byte alignment
+	dsub	sp, sp, GD_SIZE		# reserve space for gd
+	and	sp, sp, t0		# force 16 byte alignment
+	move	k0, sp			# save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	dli	t2, CONFIG_SYS_MALLOC_F_LEN
+	dsub	sp, sp, t2		# reserve space for early malloc
+	and	sp, sp, t0		# force 16 byte alignment
+#endif
 	move	fp, sp
 
+	/* Clear gd */
+	move	t0, k0
+1:
+	sw	zero, 0(t0)
+	blt	t0, t1, 1b
+	 daddi	t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	daddu	t0, k0, GD_MALLOC_BASE	# gd->malloc_base offset
+	sw	sp, 0(t0)
+#endif
+
 	dla	t9, board_init_f
 	jr	t9
 	 move	ra, zero
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
index 0497acf4a1..553da5f4ba 100644
--- a/arch/mips/cpu/mips64/time.c
+++ b/arch/mips/cpu/mips64/time.c
@@ -8,63 +8,12 @@
 #include <common.h>
 #include <asm/mipsregs.h>
 
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	 \
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
+unsigned long notrace timer_read_counter(void)
 {
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
+	return read_c0_count();
 }
 
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+ulong notrace get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return CONFIG_SYS_MIPS_TIMER_FREQ;
 }