diff options
| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2017-05-07 20:09:31 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2017-05-10 16:16:09 +0200 |
| commit | 2507f69c41d8b4f9140e3668f3a4c76a43bb76d1 (patch) | |
| tree | 5e45cb354c2b179727164f69896f85be8f222cf7 /arch/mips/dts | |
| parent | e64bdb2fcfce7e002964e72f2732920ecda4b74c (diff) | |
mips: bmips: add bcm6345-gpio driver support for BCM6358
This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/mips/dts')
| -rw-r--r-- | arch/mips/dts/brcm,bcm6358.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 48322fb143..4c94555204 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -73,6 +73,25 @@ mask = <0x1>; }; + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@fffe0100 { compatible = "brcm,bcm6345-uart"; reg = <0xfffe0100 0x18>; |