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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-02-24 07:59:38 +0100 |
| commit | e1cc4d31f889428a4ca73120951389c756404184 (patch) | |
| tree | 4a2028c750e19f5d36d0aa7545bda7cbacea9dd4 /arch/mips/include/asm/cacheops.h | |
| parent | 23d184d2fbc805bdd9fb41f2370cdce04a7894af (diff) | |
| parent | 38dac81b3d0e777f301ca98100bfbcab01d616c2 (diff) | |
Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 6464250d84..75ec380980 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -11,6 +11,19 @@ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H +#ifndef __ASSEMBLY__ + +static inline void mips_cache(int op, const volatile void *addr) +{ +#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE + __builtin_mips_cache(op, addr); +#else + __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) +#endif +} + +#endif /* !__ASSEMBLY__ */ + /* * Cache Operations available on all MIPS processors with R4000-style caches */ |