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authorPaul Burton <paul.burton@imgtec.com>2013-11-08 11:18:57 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2013-11-09 17:21:02 +0100
commit81f98bbd62b66e4a590fe6fe9b0d8231e45beffd (patch)
treeb7ea029d769b9c014983faa2c55f3e4302d1145e /arch/mips/include
parentfba6f45cdcf77985c4bf891322b5442bda1005e0 (diff)
malta: setup PIIX4 interrupt route
Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/malta.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index d8ec57cf48..e141eb0ae5 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -53,4 +53,9 @@
#define MALTA_REVISION_CORID_CORE_LV 1
#define MALTA_REVISION_CORID_CORE_FPGA6 14
+#define PCI_CFG_PIIX4_PIRQRCA 0x60
+#define PCI_CFG_PIIX4_PIRQRCB 0x61
+#define PCI_CFG_PIIX4_PIRQRCC 0x62
+#define PCI_CFG_PIIX4_PIRQRCD 0x63
+
#endif /* _MIPS_ASM_MALTA_H */