diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-06-09 13:09:51 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-06-10 12:27:29 +0200 |
| commit | a95800e881a8df837f0c4121a2cd560a4c02bd2f (patch) | |
| tree | cd113e5378ef3e0d720a97c40fabff9738467565 /arch/mips/lib/cache.c | |
| parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
Diffstat (limited to 'arch/mips/lib/cache.c')
| -rw-r--r-- | arch/mips/lib/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 5f520c069f..db81953f86 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) if (start_addr == stop) return; - cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I); + cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); } |