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authorPaul Burton <paul.burton@imgtec.com>2016-09-21 11:18:59 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-09-21 15:04:04 +0200
commit639200f6a0dcfe67e4c923b6108703e192946388 (patch)
tree2c086874eab5ecabfe7b0aac920d8608d5fbbc72 /arch/mips/lib/cache_init.S
parentd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 (diff)
MIPS: Ensure cache ops complete in mips_cache_reset
Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/lib/cache_init.S')
-rw-r--r--arch/mips/lib/cache_init.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 53e903a27e..698a5afdee 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -420,6 +420,8 @@ l2_unbypass:
#endif
return:
+ /* Ensure all cache operations complete before returning */
+ sync
jr ra
END(mips_cache_reset)