diff options
| author | Simon Glass <sjg@chromium.org> | 2020-05-10 11:40:13 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-18 21:19:23 -0400 |
| commit | cd93d625fd751d55c729c78b10f82109d56a5f1d (patch) | |
| tree | 158fd30f3d06142f6a99cbae6ed8ccb0f3be567b /arch/mips/mach-mscc/include/mach/ocelot | |
| parent | f09f1ecbe77863ecefe586ccd6000064b49105a3 (diff) | |
common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/mips/mach-mscc/include/mach/ocelot')
3 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index b2a4203644..5715ec164c 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ #define _MSCC_OCELOT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_SOFT_RST 0x8 #define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h index 4ad92214a3..50cf073eab 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h index 04cf70bec3..fb10bf2c26 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_ICPU_CFG_H_ #define _MSCC_OCELOT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 |