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| author | Tom Rini <trini@konsulko.com> | 2018-09-23 15:14:12 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-09-23 15:14:12 -0400 |
| commit | 284b27cf81da10d55070a49ee8b739f71377a4fb (patch) | |
| tree | 993c2449155eefd6ec3d6752a27c5d289ee23d46 /arch/mips/mach-mt7620/mt76xx.h | |
| parent | 9dc8d155d4e88563f572ee79aab758eb4272f3fd (diff) | |
| parent | fdd1a9ff781cda82696f8971e540e475fd1e9933 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch/mips/mach-mt7620/mt76xx.h')
| -rw-r--r-- | arch/mips/mach-mt7620/mt76xx.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mt7620/mt76xx.h new file mode 100644 index 0000000000..17473ea8f1 --- /dev/null +++ b/arch/mips/mach-mt7620/mt76xx.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese <sr@denx.de> + */ + +#ifndef __MT76XX_H +#define __MT76XX_H + +#define MT76XX_SYSCTL_BASE 0x10000000 + +#define MT76XX_CHIPID_OFFS 0x00 +#define MT76XX_CHIP_REV_ID_OFFS 0x0c +#define MT76XX_SYSCFG0_OFFS 0x10 + +#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300) +#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000) + +#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028) +#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c) +#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440) + +#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) +#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) +#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) +#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) + +#ifndef __ASSEMBLY__ +/* Prototypes */ +void ddr_calibrate(void); +#endif + +#endif |