diff options
| author | rick <rick@andestech.com> | 2017-05-18 14:37:53 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2017-05-22 14:05:46 +0800 |
| commit | b841b6e94662b3b21a56d6ecaab64dcdfb0d311c (patch) | |
| tree | 92847f53ffaeb104754e2940b32b981314627750 /arch/nds32/include/asm/arch-ae3xx/ae3xx.h | |
| parent | f5076f869855045e527de7f1367c65f55a2b1448 (diff) | |
nds32: Support AE3XX platform.
Support Andestech AE3xx platform: serial, timer device tree flow.
Signed-off-by: rick <rick@andestech.com>
Diffstat (limited to 'arch/nds32/include/asm/arch-ae3xx/ae3xx.h')
| -rw-r--r-- | arch/nds32/include/asm/arch-ae3xx/ae3xx.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h new file mode 100644 index 0000000000..b074e8489a --- /dev/null +++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AE3XX_H +#define __AE3XX_H + +/* Hardware register bases */ + +/* Static Memory Controller (SRAM) */ +#define CONFIG_FTSMC020_BASE 0xe0400000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0xf0c00000 +/* AHB-to-APB Bridge */ +#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 +/* Reserved */ +#define CONFIG_RESERVED_01_BASE 0xe0500000 +/* Reserved */ +#define CONFIG_RESERVED_02_BASE 0xf0800000 +/* Reserved */ +#define CONFIG_RESERVED_03_BASE 0xf0900000 +/* Ethernet */ +#define CONFIG_FTMAC100_BASE 0xe0100000 +/* Reserved */ +#define CONFIG_RESERVED_04_BASE 0xf1000000 + +/* APB Device definitions */ + +/* UART1 */ +#define CONFIG_FTUART010_01_BASE 0xf0200000 +/* UART2 */ +#define CONFIG_FTUART010_02_BASE 0xf0300000 +/* Counter/Timers */ +#define CONFIG_FTTMR010_BASE 0xf0400000 +/* Watchdog Timer */ +#define CONFIG_FTWDT010_BASE 0xf0500000 +/* Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0xf0600000 +/* GPIO */ +#define CONFIG_FTGPIO010_BASE 0xf0700000 +/* I2C */ +#define CONFIG_FTIIC010_BASE 0xf0a00000 +/* SD Controller */ +#define CONFIG_FTSDC010_BASE 0xf0e00000 + +/* The following address was not defined in Linux */ + +/* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_FTSSP010_01_BASE 0xf0d00000 +#endif /* __AE3XX_H */ |