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| author | Chuanhua Han <chuanhua.han@nxp.com> | 2019-08-01 16:36:57 +0800 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-22 09:07:36 +0530 |
| commit | 1748990ab2a0e995beeed6b3856335f579bb77d9 (patch) | |
| tree | 814428e029da8ef7f4487836b9d765ffe5445b26 /arch/nios2/cpu/traps.c | |
| parent | a02a9421f4ac96e7a3f441d2388e9945a9d84e05 (diff) | |
armv8: ls1088aqds: support DSPI mode by hwconfig
BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used
to control SPI and other IP signal routing.
USBOSC:
0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz.
SPI devices are unusable in this mode.
1= SPI_CLK used as SPI clock.
SPI devices are usable in this mode. USB block is clocked from
internal sources
SPR[3:2]:
SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]):
00= SDHC/eMMC 8-bit
01= SD Card Rev 2.0/3.0
10= SPI on-board memory
11= TDM Riser / SPI off-board connector.
The default value is 00 if an SDCard/eMMC card is selected as the boot
device.
SPR[1:0]:
SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]):
00= SDHC Sync loop
01= TDM Riser / SPI off-board connector.
10= SPI on-board memory.
11= SPI off-board connector.
By default, the SPI feature is not available, so we need to configure
the above register fields to select the route to the SPI feature.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/nios2/cpu/traps.c')
0 files changed, 0 insertions, 0 deletions