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authorDarwin Dingel <darwin.dingel@alliedtelesis.co.nz>2016-10-25 09:48:01 +1300
committerYork Sun <york.sun@nxp.com>2017-01-24 13:28:02 -0800
commit06ad970b53a3d6aa122685e6142a04908434a8ef (patch)
tree421d254147fd51429b5d09eead885b9d87d7a526 /arch/powerpc/cpu/mpc85xx/Kconfig
parent0c9e85f67cd86d2d7a3424ea3ebff0e6db7a3915 (diff)
powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907
Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: York Sun <york.sun@nxp.com> [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/Kconfig')
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 704f65b093..b0f34b6f15 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -365,6 +365,7 @@ config ARCH_B4860
select SYS_FSL_ERRATUM_A007075
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -830,6 +831,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
@@ -891,6 +893,7 @@ config ARCH_T4240
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -1081,6 +1084,9 @@ config SYS_FSL_ERRATUM_A007212
config SYS_FSL_ERRATUM_A007798
bool
+config SYS_FSL_ERRATUM_A007907
+ bool
+
config SYS_FSL_ERRATUM_A008044
bool