diff options
| author | Jaiprakash Singh <Jaiprakash.singh@nxp.com> | 2020-06-02 12:44:02 +0530 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-06-04 18:53:20 +0530 |
| commit | 164a5af43635c63ea2459d4c87a1a4b16acd689a (patch) | |
| tree | a3e7dee7d322a108e1986ef915e13486a2b63425 /arch/powerpc/cpu/mpc85xx/Kconfig | |
| parent | 73af094c8444ea6affc607d3ca7704419b3fbfd8 (diff) | |
ddr: Rework errata A008109, A008378, 009942 workaround
Move errata A008109, A008378, 009942 workaround implementation from
compute_fsl_memctl_config_regs() to fsl_ddr_set_memctl_regs()
and add register write after each workaround implementation.
Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/Kconfig')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 5bd69d51cb..285cc56799 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -996,6 +996,7 @@ config ARCH_T1023 select FSL_LAW select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 @@ -1016,6 +1017,7 @@ config ARCH_T1024 select FSL_LAW select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 @@ -1091,6 +1093,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 + select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select FSL_PCIE_RESET @@ -1169,6 +1172,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 + select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC |