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authorShaveta Leekha <shaveta@freescale.com>2014-02-26 16:08:22 +0530
committerYork Sun <yorksun@freescale.com>2014-03-07 14:52:01 -0800
commit7af9a07403e80415d097b4175616c7a7686b7deb (patch)
tree654dc903d92e67b3854338e970e17cb3f3fb86ff /arch/powerpc/cpu/mpc85xx/cpu_init.c
parentc4930b1a0ee5a35c49de10e0289f9c8253e78848 (diff)
powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
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