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| author | York Sun <yorksun@freescale.com> | 2013-09-16 12:49:31 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
| commit | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch) | |
| tree | 8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | |
| parent | e512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff) | |
powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.
Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c')
0 files changed, 0 insertions, 0 deletions