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| author | Jaiprakash Singh <b44839@freescale.com> | 2015-05-22 15:21:07 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-28 14:41:16 -0700 |
| commit | 7842950f7c05aa9d901308d149ad3d67237bb315 (patch) | |
| tree | d9cf2448a4e75d77029e9676b319acb1be2bae6d /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | 1ff10a87c32acf8ec4e8676c4e01dbcc8b255ec3 (diff) | |
powerpc/T102xRDB: Enable ifc nand ecc encode and decode
IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
0 files changed, 0 insertions, 0 deletions