diff options
| author | York Sun <yorksun@freescale.com> | 2015-08-17 13:31:52 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-09-01 20:42:54 -0500 |
| commit | 2becdc6f9df470b6c768d59509e661d1066b38c7 (patch) | |
| tree | e59d49b8c3e661e07a50ca475ad17a3030735cf4 /arch/powerpc/cpu/mpc85xx | |
| parent | b3142e2cf82ab207a88868264d709a40e83f065e (diff) | |
powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index a70fb711c7..d867e2a767 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1116,7 +1116,11 @@ switch_as: li r0,0 1: dcbz r0,r3 - dcbtls 0,r0,r3 +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ + dcbtls 2, r0, r3 +#else + dcbtls 0, r0, r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b @@ -1727,7 +1731,11 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 +#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ + dcblc 2, r0, r3 +#else dcblc r0,r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync |