diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2013-08-15 09:31:47 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-20 10:47:07 -0700 |
| commit | 424bf94273b2cd0171eca7ed5619b211f1b96d8f (patch) | |
| tree | fad1af231d9c332afef5915d68d6b45c02762adc /arch/powerpc/cpu/mpc85xx | |
| parent | e1a2a3401956f546ac18cdc58716860286868425 (diff) | |
powerpc/sec: Add workaround for SEC A-003571
Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 |
2 files changed, 13 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index cbb443fd2c..8a2a3ee76c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -245,6 +245,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A003571 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 puts("Work-around for Erratum A-005812 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index c6e09ca905..6036333eaa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -357,7 +357,9 @@ int cpu_init_r(void) extern int spin_table_compat; const char *spin; #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* @@ -548,6 +550,12 @@ skip_l2: fsl_serdes_init(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 +#define MCFGR_AXIPIPE 0x000000f0 + if (IS_SVR_REV(svr, 1, 0)) + clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; |