diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:25 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:28 -0500 |
| commit | eb5394120643922626f18e5fe7b0b3dc0ed43b9a (patch) | |
| tree | 968121a3577cf3c8e14bd435d9c8c303140f3cd1 /arch/powerpc/cpu/mpc86xx/fdt.c | |
| parent | f31cfd19253713eea59311dec9e99df5d43b2db9 (diff) | |
powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx/fdt.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc86xx/fdt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 61f5110b7d..2f955fe930 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP int off; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, |