powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>

1 files changed, 63 insertions, 60 deletions

diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 28cc182957..5cfc8c189c 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static char *cpu_warning = "\n         " \
 	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
 
-static int check_CPU (long clock, uint pvr, uint immr)
+static int check_CPU(long clock, uint pvr, uint immr)
 {
 	char *id_str =
 	NULL;
@@ -73,22 +73,25 @@ static int check_CPU (long clock, uint pvr, uint immr)
 			id_str =
 		"PC866x"; /* Unknown chip from MPC866 family */
 		break;
-	case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
+	case 0x09000000:
+		pre = 'M'; mid = suf = ""; m = 1;
 		if (id_str == NULL)
 			id_str = "PC885"; /* 870/875/880/885 */
 		break;
 
-	default: suf = NULL; break;
+	default:
+		suf = NULL;
+		break;
 	}
 
 	if (id_str == NULL)
 		id_str = "PC86x";	/* Unknown 86x chip */
 	if (suf)
-		printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
+		printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
 	else
-		printf ("unknown M%s (0x%08x)", id_str, k);
+		printf("unknown M%s (0x%08x)", id_str, k);
 
-	printf (" at %s MHz: ", strmhz (buf, clock));
+	printf(" at %s MHz: ", strmhz(buf, clock));
 
 	print_size(checkicache(), " I-Cache ");
 	print_size(checkdcache(), " D-Cache");
@@ -97,64 +100,63 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
 	out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
 	if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
-		printf (" FEC present");
+		printf(" FEC present");
 
-	if (!m) {
-		puts (cpu_warning);
-	}
+	if (!m)
+		puts(cpu_warning);
 
-	putc ('\n');
+	putc('\n');
 
 	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
 
-int checkcpu (void)
+int checkcpu(void)
 {
 	ulong clock = gd->cpu_clk;
-	uint immr = get_immr (0);	/* Return full IMMR contents */
-	uint pvr = get_pvr ();
+	uint immr = get_immr(0);	/* Return full IMMR contents */
+	uint pvr = get_pvr();
 
-	puts ("CPU:   ");
+	puts("CPU:   ");
 
-	return check_CPU (clock, pvr, immr);
+	return check_CPU(clock, pvr, immr);
 }
 
 /* ------------------------------------------------------------------------- */
 /* L1 i-cache                                                                */
 
-int checkicache (void)
+int checkicache(void)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	memctl8xx_t __iomem *memctl = &immap->im_memctl;
-	u32 cacheon = rd_ic_cst () & IDC_ENABLED;
+	u32 cacheon = rd_ic_cst() & IDC_ENABLED;
 	/* probe in flash memoryarea */
 	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
 	u32 m;
 	u32 lines = -1;
 
-	wr_ic_cst (IDC_UNALL);
-	wr_ic_cst (IDC_INVALL);
-	wr_ic_cst (IDC_DISABLE);
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
+	wr_ic_cst(IDC_DISABLE);
 	__asm__ volatile ("isync");
 
-	while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
-		wr_ic_adr (k);
-		wr_ic_cst (IDC_LDLCK);
+	while (!((m = rd_ic_cst()) & IDC_CERR2)) {
+		wr_ic_adr(k);
+		wr_ic_cst(IDC_LDLCK);
 		__asm__ volatile ("isync");
 
 		lines++;
-		k += 0x10;				/* the number of bytes in a cacheline */
+		k += 0x10;	/* the number of bytes in a cacheline */
 	}
 
-	wr_ic_cst (IDC_UNALL);
-	wr_ic_cst (IDC_INVALL);
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
 
 	if (cacheon)
-		wr_ic_cst (IDC_ENABLE);
+		wr_ic_cst(IDC_ENABLE);
 	else
-		wr_ic_cst (IDC_DISABLE);
+		wr_ic_cst(IDC_DISABLE);
 
 	__asm__ volatile ("isync");
 
@@ -165,41 +167,41 @@ int checkicache (void)
 /* L1 d-cache                                                                */
 /* call with cache disabled                                                  */
 
-int checkdcache (void)
+int checkdcache(void)
 {
 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
 	memctl8xx_t __iomem *memctl = &immap->im_memctl;
-	u32 cacheon = rd_dc_cst () & IDC_ENABLED;
+	u32 cacheon = rd_dc_cst() & IDC_ENABLED;
 	/* probe in flash memoryarea */
 	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
 	u32 m;
 	u32 lines = -1;
 
-	wr_dc_cst (IDC_UNALL);
-	wr_dc_cst (IDC_INVALL);
-	wr_dc_cst (IDC_DISABLE);
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
+	wr_dc_cst(IDC_DISABLE);
 
-	while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
-		wr_dc_adr (k);
-		wr_dc_cst (IDC_LDLCK);
+	while (!((m = rd_dc_cst()) & IDC_CERR2)) {
+		wr_dc_adr(k);
+		wr_dc_cst(IDC_LDLCK);
 		lines++;
 		k += 0x10;	/* the number of bytes in a cacheline */
 	}
 
-	wr_dc_cst (IDC_UNALL);
-	wr_dc_cst (IDC_INVALL);
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
 
 	if (cacheon)
-		wr_dc_cst (IDC_ENABLE);
+		wr_dc_cst(IDC_ENABLE);
 	else
-		wr_dc_cst (IDC_DISABLE);
+		wr_dc_cst(IDC_DISABLE);
 
 	return lines << 4;
 };
 
 /* ------------------------------------------------------------------------- */
 
-void upmconfig (uint upm, uint * table, uint size)
+void upmconfig(uint upm, uint *table, uint size)
 {
 	uint i;
 	uint addr = 0;
@@ -215,7 +217,7 @@ void upmconfig (uint upm, uint * table, uint size)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong msr, addr;
 
@@ -226,10 +228,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/* Interrupts and MMU off */
 	__asm__ volatile ("mtspr    81, 0");
-	__asm__ volatile ("mfmsr    %0":"=r" (msr));
+	__asm__ volatile ("mfmsr    %0" : "=r" (msr));
 
 	msr &= ~0x1030;
-	__asm__ volatile ("mtmsr    %0"::"r" (msr));
+	__asm__ volatile ("mtmsr    %0" : : "r" (msr));
 
 	/*
 	 * Trying to execute the next instruction at a non-existing address
@@ -239,14 +241,15 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	addr = CONFIG_SYS_RESET_ADDRESS;
 #else
 	/*
-	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
-	 * - sizeof (ulong) is usually a valid address. Better pick an address
-	 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
+	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+	 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
+	 * Better pick an address known to be invalid on your system and assign
+	 * it to CONFIG_SYS_RESET_ADDRESS.
 	 * "(ulong)-1" used to be a good choice for many systems...
 	 */
-	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
+	addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
 #endif
-	((void (*)(void)) addr) ();
+	((void (*)(void)) addr)();
 	return 1;
 }
 
@@ -257,14 +260,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  *
  * See sections 14.2 and 14.6 of the User's Manual
  */
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
 {
-	uint immr = get_immr (0);	/* Return full IMMR contents */
+	uint immr = get_immr(0);	/* Return full IMMR contents */
 	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
 	ulong oscclk, factor, pll;
 
 	if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
-		return (gd->cpu_clk / 16);
+		return gd->cpu_clk / 16;
 
 	pll = in_be32(&immap->im_clkrst.car_plprcr);
 
@@ -281,28 +284,28 @@ unsigned long get_tbclk (void)
 	 *	     (PDF + 1) * 2^S
 	 *
 	 */
-		factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
-			(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
+	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
+		 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
 
 	oscclk = gd->cpu_clk / factor;
 
 	if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
 	    factor > 2)
-		return (oscclk / 4);
+		return oscclk / 4;
 
-	return (oscclk / 16);
+	return oscclk / 16;
 }
 
 /* ------------------------------------------------------------------------- */
 
 #if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
+void watchdog_reset(void)
 {
-	int re_enable = disable_interrupts ();
+	int re_enable = disable_interrupts();
 
 	reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
 	if (re_enable)
-		enable_interrupts ();
+		enable_interrupts();
 }
 #endif /* CONFIG_WATCHDOG */