diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:48 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:39 -0700 |
| commit | c63e137014cf148bc1d234128941dccee3d519ae (patch) | |
| tree | afb69c22c33459d14a174973083e2a70e5f49ea7 /arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | |
| parent | b61e06156660579ea6e248abd2506ebdd85e7a14 (diff) | |
powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/ddr.h')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 4dd55fc4c3..c173a5a74b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -96,7 +96,7 @@ unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); + unsigned int ctrl_num, int step); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, |