Merge branch 'master' of /home/wd/git/u-boot/custodians

* 'master' of /home/wd/git/u-boot/custodians:
  powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
  powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
  cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
  PowerPC: correct the SATA for p1/p2 rdb-pc platform
  powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
  powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
  powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
  powerpc/corenet_ds: Slave module for boot from SRIO
  powerpc/corenet_ds: Master module for boot from SRIO
  powerpc/corenet_ds: Document for the boot from SRIO
  powerpc/corenet_ds: Correct the compilation errors about ENV
  powerpc/srio: Rewrite the struct ccsr_rio
  powerpc/85xx:Fix lds for nand boot debug info
  powerpc/p2041rdb: add env in NAND support
  powerpc/p2041rdb: add NAND and NAND boot support
  powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
  powerpc/85xx:Avoid vector table compilation for nand_spl
  powerpc/85xx:Fix IVORs addr after vector table relocation
  powerpc/85xx:Avoid hardcoded vector address for IVORs
  powerpc/p1023rds: Disable nor flash node and enable nand flash node

1 files changed, 210 insertions, 0 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328067..c7f394972b 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,16 @@
 #include <config.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
+#include <asm/fsl_srio.h>
+
+#define SRIO_PORT_ACCEPT_ALL 0x10000001
+#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
+#define SRIO_LCSBA1CSR 0x60000000
 
 #if defined(CONFIG_FSL_CORENET)
 	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +94,203 @@ void srio_init(void)
 		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
 	}
 }
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+	/* set port accept-all */
+	out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+				SRIO_PORT_ACCEPT_ALL);
+
+	debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
+			CONFIG_SRIOBOOT_MASTER_PORT);
+	/* configure inbound window for slave's u-boot image */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+	/* configure inbound window for slave's u-boot image */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+	/* configure inbound window for slave's ucode */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+			(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+	/* configure inbound window for slave's ENV */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
+			"Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
+			CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
+}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+	u32 escsr;
+	debug("SRIOBOOT - MASTER: "
+			"Check the port status and release slave core ...\n");
+
+	escsr = in_be32((void *)&srio->lp_serial
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+	if (escsr & 0x2) {
+		if (escsr & 0x10100) {
+			debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
+					CONFIG_SRIOBOOT_MASTER_PORT);
+		} else {
+			debug("SRIOBOOT - MASTER: "
+					"Port [ %d ] is ready, now release slave's core ...\n",
+					CONFIG_SRIOBOOT_MASTER_PORT);
+			/*
+			 * configure outbound window
+			 * with maintenance attribute to set slave's LCSBA1CSR
+			 */
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[1].rowtar, 0);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[1].rowtear, 0);
+			if (CONFIG_SRIOBOOT_MASTER_PORT)
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowbar,
+					CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+			else
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowbar,
+					CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+			out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowar,
+					SRIO_OB_ATMU_AR_MAINT
+					| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+			/*
+			 * configure outbound window
+			 * with R/W attribute to set slave's BRR
+			 */
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowtar,
+				SRIO_LCSBA1CSR >> 9);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowtear, 0);
+			if (CONFIG_SRIOBOOT_MASTER_PORT)
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[2].rowbar,
+					(CONFIG_SYS_SRIO2_MEM_PHYS
+					+ SRIO_MAINT_WIN_SIZE) >> 12);
+			else
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[2].rowbar,
+					(CONFIG_SYS_SRIO1_MEM_PHYS
+					+ SRIO_MAINT_WIN_SIZE) >> 12);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowar,
+				SRIO_OB_ATMU_AR_RW
+				| atmu_size_mask(SRIO_RW_WIN_SIZE));
+
+			/*
+			 * Set the LCSBA1CSR register in slave
+			 * by the maint-outbound window
+			 */
+			if (CONFIG_SRIOBOOT_MASTER_PORT) {
+				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET,
+					SRIO_LCSBA1CSR);
+				while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET)
+					!= SRIO_LCSBA1CSR)
+					;
+				/*
+				 * And then set the BRR register
+				 * to release slave core
+				 */
+				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_MAINT_WIN_SIZE
+					+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+					CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+			} else {
+				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET,
+					SRIO_LCSBA1CSR);
+				while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET)
+					!= SRIO_LCSBA1CSR)
+					;
+				/*
+				 * And then set the BRR register
+				 * to release slave core
+				 */
+				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_MAINT_WIN_SIZE
+					+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+					CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+			}
+			debug("SRIOBOOT - MASTER: "
+					"Release slave successfully! Now the slave should start up!\n");
+		}
+	} else
+		debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
+				CONFIG_SRIOBOOT_MASTER_PORT);
+}
+#endif
+#endif