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authorWolfgang Denk <wd@denx.de>2011-04-05 12:24:20 +0200
committerWolfgang Denk <wd@denx.de>2011-04-05 12:24:20 +0200
commit4db2fa7f9446d0f2fe8db3d62184b1212fe22707 (patch)
treebc62cbfc14296551caebda626db7a90fef9ae844 /arch/powerpc/cpu/mpc8xxx
parent75df0d594990875419121c6f8687472ac9f4ae7a (diff)
parent7d3053fbf16caad4745f42f7ae3e38e9d3e964b5 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/Makefile1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c14
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c4
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr.h1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c23
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c43
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c11
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c63
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/util.c60
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fsl_ifc.c84
10 files changed, 242 insertions, 62 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 5dfd65b882..4ae26e4210 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -15,6 +15,7 @@ COBJS-y += cpu.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
COBJS-$(CONFIG_SYS_SRIO) += srio.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 4335fb4f31..39b304ae99 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -71,15 +71,27 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1014, P1014_E, 1),
CPU_TYPE_ENTRY(P1014, P1014, 1),
- CPU_TYPE_ENTRY(P1013, P1013_E, 1),
+ CPU_TYPE_ENTRY(P1015, P1015_E, 1),
+ CPU_TYPE_ENTRY(P1015, P1015, 1),
+ CPU_TYPE_ENTRY(P1016, P1016_E, 1),
+ CPU_TYPE_ENTRY(P1016, P1016, 1),
+ CPU_TYPE_ENTRY(P1017, P1017, 1),
+ CPU_TYPE_ENTRY(P1017, P1017, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1021, P1021_E, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
CPU_TYPE_ENTRY(P1022, P1022_E, 2),
+ CPU_TYPE_ENTRY(P1023, P1023, 2),
+ CPU_TYPE_ENTRY(P1023, P1023_E, 2),
+ CPU_TYPE_ENTRY(P1024, P1024, 2),
+ CPU_TYPE_ENTRY(P1024, P1024_E, 2),
+ CPU_TYPE_ENTRY(P1025, P1025, 2),
+ CPU_TYPE_ENTRY(P1025, P1025_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index cefabe769f..02d069c9ec 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
- unsigned int data_rate = fsl_ddr_get_mem_data_rate();
+ unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
@@ -1305,7 +1305,7 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
{
if (popts->addr_hash) {
ddr->ddr_eor = 0x40000000; /* address hash enable */
- puts("Addess hashing enabled.\n");
+ puts("Address hashing enabled.\n");
}
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index c7c12c1c2f..1e866fe035 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
extern unsigned int mclk_to_picos(unsigned int mclk);
extern unsigned int get_memory_clk_period_ps(void);
extern unsigned int picos_to_mclk(unsigned int picos);
-extern unsigned int fsl_ddr_get_mem_data_rate(void);
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index dcb37cea1f..b565e338ad 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -250,24 +250,27 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
pdimm->primary_sdram_width = spd->primw;
pdimm->ec_sdram_width = spd->ecw;
- /* FIXME: what about registered SO-DIMM? */
+ /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
switch (spd->dimm_type) {
- case 0x01: /* RDIMM */
- case 0x10: /* Mini-RDIMM */
- pdimm->registered_dimm = 1; /* register buffered */
+ case DDR2_SPD_DIMMTYPE_RDIMM:
+ case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
+ case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
+ /* Registered/buffered DIMMs */
+ pdimm->registered_dimm = 1;
break;
- case 0x02: /* UDIMM */
- case 0x04: /* SO-DIMM */
- case 0x08: /* Micro-DIMM */
- case 0x20: /* Mini-UDIMM */
- pdimm->registered_dimm = 0; /* unbuffered */
+ case DDR2_SPD_DIMMTYPE_UDIMM:
+ case DDR2_SPD_DIMMTYPE_SO_DIMM:
+ case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
+ case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
+ /* Unbuffered DIMMs */
+ pdimm->registered_dimm = 0;
break;
+ case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
default:
printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
return 1;
- break;
}
/* SDRAM device parameters */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 29cea53266..756b15f7ab 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -128,24 +128,32 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
pdimm->data_width = pdimm->primary_sdram_width
+ pdimm->ec_sdram_width;
- switch (spd->module_type & 0xf) {
- case 0x01: /* RDIMM */
- case 0x05: /* Mini-RDIMM */
- pdimm->registered_dimm = 1; /* register buffered */
+ /* These are the types defined by the JEDEC DDR3 SPD spec */
+ pdimm->mirrored_dimm = 0;
+ pdimm->registered_dimm = 0;
+ switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
+ case DDR3_SPD_MODULETYPE_RDIMM:
+ case DDR3_SPD_MODULETYPE_MINI_RDIMM:
+ /* Registered/buffered DIMMs */
+ pdimm->registered_dimm = 1;
for (i = 0; i < 16; i += 2) {
- pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F;
- pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F;
+ u8 rcw = spd->mod_section.registered.rcw[i/2];
+ pdimm->rcw[i] = (rcw >> 0) & 0x0F;
+ pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
}
break;
- case 0x02: /* UDIMM */
- case 0x03: /* SO-DIMM */
- case 0x04: /* Micro-DIMM */
- case 0x06: /* Mini-UDIMM */
- pdimm->registered_dimm = 0; /* unbuffered */
+
+ case DDR3_SPD_MODULETYPE_UDIMM:
+ case DDR3_SPD_MODULETYPE_SO_DIMM:
+ case DDR3_SPD_MODULETYPE_MICRO_DIMM:
+ case DDR3_SPD_MODULETYPE_MINI_UDIMM:
+ /* Unbuffered DIMMs */
+ if (spd->mod_section.unbuffered.addr_mapping & 0x1)
+ pdimm->mirrored_dimm = 1;
break;
default:
- printf("unknown dimm_type 0x%02X\n", spd->module_type);
+ printf("unknown module_type 0x%02X\n", spd->module_type);
return 1;
}
@@ -303,16 +311,5 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
* mtb_ps;
- /*
- * We need check the address mirror for unbuffered DIMM
- * If SPD indicate the address map mirror, The DDR controller
- * need care it.
- */
- if ((spd->module_type == SPD_MODULETYPE_UDIMM) ||
- (spd->module_type == SPD_MODULETYPE_SODIMM) ||
- (spd->module_type == SPD_MODULETYPE_MICRODIMM) ||
- (spd->module_type == SPD_MODULETYPE_MINIUDIMM))
- pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1;
-
return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 8b31ec0cfa..00f3d6c600 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -207,10 +207,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
temp1 = temp2 = 0;
for (i = 0; i < number_of_dimms; i++) {
if (dimm_params[i].n_ranks) {
- if (dimm_params[i].registered_dimm)
+ if (dimm_params[i].registered_dimm) {
temp1 = 1;
- if (!dimm_params[i].registered_dimm)
+ printf("Detected RDIMM %s\n",
+ dimm_params[i].mpart);
+ } else {
temp2 = 1;
+ printf("Detected UDIMM %s\n",
+ dimm_params[i].mpart);
+ }
}
}
@@ -218,10 +223,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
outpdimm->all_DIMMs_unbuffered = 0;
if (temp1 && !temp2) {
outpdimm->all_DIMMs_registered = 1;
- printf("Detected RDIMM(s)\n");
} else if (!temp1 && temp2) {
outpdimm->all_DIMMs_unbuffered = 1;
- printf("Detected UDIMM(s)\n");
} else {
printf("ERROR: Mix of registered buffered and unbuffered "
"DIMMs detected!\n");
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index bb96d66a9d..c8fa123539 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include "ddr.h"
@@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar(
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
-/* Board-specific functions defined in each board's ddr.c */
-extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num);
+#if defined(SPD_EEPROM_ADDRESS) || \
+ defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
+ defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
+#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS,
+};
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
+ [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
+};
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+ [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
+ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
+ [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
+ [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
+};
+#endif
+
+static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+
+ if (ret) {
+ printf("DDR: failed to read SPD from address %u\n", i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+__attribute__((weak, alias("__get_spd")))
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
+
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ i2c_address = spd_i2c_addr[ctrl_num][i];
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+#else
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+}
+#endif /* SPD_EEPROM_ADDRESSx */
/*
* ASSUMPTIONS:
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 1e2d921286..02908b4561 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -8,10 +8,16 @@
#include <common.h>
#include <asm/fsl_law.h>
+#include <div64.h>
#include "ddr.h"
-unsigned int fsl_ddr_get_mem_data_rate(void);
+/* To avoid 64-bit full-divides, we factor this here */
+#define ULL_2e12 2000000000000ULL
+#define UL_5pow12 244140625UL
+#define UL_2pow13 (1UL << 13)
+
+#define ULL_8Fs 0xFFFFFFFFULL
/*
* Round mclk_ps to nearest 10 ps in memory controller code.
@@ -22,35 +28,51 @@ unsigned int fsl_ddr_get_mem_data_rate(void);
*/
unsigned int get_memory_clk_period_ps(void)
{
- unsigned int mclk_ps;
+ unsigned int data_rate = get_ddr_freq(0);
+ unsigned int result;
+
+ /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
+ unsigned long long mclk_ps = ULL_2e12;
+
+ /* Add 5*data_rate, for rounding */
+ mclk_ps += 5*(unsigned long long)data_rate;
- mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
- /* round to nearest 10 ps */
- return 10 * ((mclk_ps + 5) / 10);
+ /* Now perform the big divide, the result fits in 32-bits */
+ do_div(mclk_ps, data_rate);
+ result = mclk_ps;
+
+ /* We still need to round to 10ps */
+ return 10 * (result/10);
}
/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
unsigned int picos_to_mclk(unsigned int picos)
{
- const unsigned long long ULL_2e12 = 2000000000000ULL;
- const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
- unsigned long long clks;
- unsigned long long clks_temp;
+ unsigned long long clks, clks_rem;
+ /* Short circuit for zero picos */
if (!picos)
return 0;
- clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
- clks_temp = clks;
- clks = clks / ULL_2e12;
- if (clks_temp % ULL_2e12) {
+ /* First multiply the time by the data rate (32x32 => 64) */
+ clks = picos * (unsigned long long)get_ddr_freq(0);
+
+ /*
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder).
+ */
+ clks_rem = do_div(clks, UL_5pow12);
+ clks_rem <<= 13;
+ clks_rem |= clks & (UL_2pow13-1);
+ clks >>= 13;
+
+ /* If we had a remainder, then round up */
+ if (clks_rem)
clks++;
- }
- if (clks > ULL_8Fs) {
+ /* Clamp to the maximum representable value */
+ if (clks > ULL_8Fs)
clks = ULL_8Fs;
- }
-
return (unsigned int) clks;
}
@@ -141,6 +163,8 @@ void board_add_ram_info(int use_default)
if (sdram_cfg & SDRAM_CFG_32_BE)
puts(", 32-bit");
+ else if (sdram_cfg & SDRAM_CFG_16_BE)
+ puts(", 16-bit");
else
puts(", 64-bit");
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
new file mode 100644
index 0000000000..39a455638f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_ifc.h>
+
+void print_ifc_regs(void)
+{
+ int i, j;
+
+ printf("IFC Controller Registers\n");
+ for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+ printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
+ i, get_ifc_cspr(i), i, get_ifc_amask(i),
+ i, get_ifc_csor(i));
+ for (j = 0; j < 4; j++)
+ printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
+ }
+}
+
+void init_early_memctl_regs(void)
+{
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+ set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+ set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+
+ set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+#endif
+
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+ set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
+ set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
+ set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+
+ set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+#endif
+
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+ set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
+ set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+ set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+
+ set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+
+#endif
+
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+ set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
+ set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+ set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+
+ set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+#endif
+}