diff options
| author | Valentin Longchamp <valentin.longchamp@keymile.com> | 2015-03-27 16:07:32 +0100 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:24:42 -0700 |
| commit | ac337168ad81a18e768e5e3cfff8d229adeb2b25 (patch) | |
| tree | 0170438bc190b71d7dc82c6f8f8863923e67d77d /arch/powerpc/cpu/ppc4xx/cache.S | |
| parent | e8a7f1c32b55f48408a10cded2663b3f578d02e2 (diff) | |
powerpc: add 2 common dcache assembly functions
This patch defines the 2 flush_dcache_range and invalidate_dcache_range
functions for all the powerpc architecture. Their implementation is
borrowed from the kernel's misc_32.S file and replace the ones from
mpc86xx and ppc4xx since they were equivalent.
This is a fix for the problem introduced by this patch:
http://patchwork.ozlabs.org/patch/448849/
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/cache.S')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/cache.S | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S index 2714c2f938..93e83662ee 100644 --- a/arch/powerpc/cpu/ppc4xx/cache.S +++ b/arch/powerpc/cpu/ppc4xx/cache.S @@ -74,49 +74,6 @@ _GLOBAL(clean_dcache_range) blr /* - * Write any modified data cache blocks out to memory and invalidate them. - * Does not invalidate the corresponding instruction cache blocks. - * - * flush_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_dcache_range) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - -1: dcbf 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Like above, but invalidate the D-cache. This is used by the 8xx - * to invalidate the cache so the PPC core doesn't get stale data - * from the CPM (no cache snooping here :-). - * - * invalidate_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(invalidate_dcache_range) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - -1: dcbi 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbi's to get to ram */ - blr - -/* * 40x cores have 8K or 16K dcache and 32 byte line size. * 44x has a 32K dcache and 32 byte line size. * 8xx has 1, 2, 4, 8K variants. |