diff options
| author | Dave Liu <daveliu@freescale.com> | 2013-11-28 14:58:08 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-12-04 14:54:10 -0800 |
| commit | 24936ed1c9a19ff855e00a37ee94ecf3941743ee (patch) | |
| tree | 76cdf94c68a6663f98c7ad3735375ce45afe7a40 /arch/powerpc/cpu | |
| parent | f44483b57c49282299da0e5c10073b909cdad979 (diff) | |
powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6a81fa73e4..db84d10c5b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -886,7 +886,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ |